ASIC Physical Design Standard-Cell Design Flow

1 ASIC Physical DesignStandard-Cell Design FlowUsing the Cadence InnovusDigital implementation SystemASIC Physical Design (Standard Cell)(can also do full custom layout)FloorplanChip/BlockPlace & RouteStd. CellsComponent-Level Verilog NetlistIC Mask DataDesign RuleCheckStd. CellLayoutsCadence Innovus Digital implementation SystemADiT/Eldo Simulation ModelBackannotateSchematicGenerateMask DataLayout RulesProcess DataLibrariesCalibreCalibreCalibreNetlis t-to-layoutdesign flowSynopsys JupiterXT Cadence SOC Innovus InnovusDigital implementation (EDI) System GUIEDI Design flowFloorplan ( flat ) through implementationDesign Import (specify input files)File > Design ImportGate-level netlist Verilog file(s) Physical data (LEF)Technology CellsIO pin planningPower planningTiming data andconstraintsExecutes init_designcommand to load files Verilog gate-level netlist(s) Gates from the standard cell library Design can be hierarchical or flat Tclcommands.

2 Set design_netlisttypeverilogset init_verilog[list ]set init_design_set_top1set init_top_cell top 0 to auto-assign top cellspecify if above = 1 Physical /Technology Library Libraries in LEF (Library Exchange Format) Technology Library Technology-specific characterizations of metal layers, vias, etc. Standard Cell Library Abstract view of each cell (box, pins, obstructions) Includes metal layers for pins (read tech. library first!) Tclcommand:set init_lef_file{ \*/ \*/std_ \}For * insert /class/ELEC6250/cmos8hpSetting up MMMC analysis# Multi-Mode/Multi-Corner (MMMC) Analysis Setup# Configure 1-corner single-model MMMC# Timing constraints file from synthesiscreate_constraint_mode-name CONSTRAINTS -sdc_files{ ../ }# Create operating condition (P-V-T) for the timing librarycreate_op_cond-name OPcondition\-library_file{/class/ELEC625 0/cmos8hp/std_ } \-P {1} -V { } -T {25}# Use typical timing library file for this designcreate_library_set-name TYPlib\-timing {/ class/ELEC6250/cmos8hp/std_ }# Create RC corner from capacitance table(s)create_rc_corner-name RCcorner\-cap_table/class/ELEC6250/IBM_P DK/BiCMOS8HP_Fire_Ice/bicmos8hp_cadence_ 20160215/ \-T {25}# Multi-Mode/Multi-Corner (MMMC)

3 Analysis Setup# Configure 1-corner single-model MMMC# Delay corner = timing library plus rc corner# Worst-case corner = max delay/affects setuptimes# Best-case corner = min delay/affects holdtimes# For 1-corner use typical values for bothcreate_delay_corner-name DELAY corner\-library_setTYPlib\-rc_cornerRCco rner# Analysis view = delay corner matched to constraintscreate_analysis_view-name TYPview\-delay_corner{DELAY corner} \-constraint_mode{CONSTRAINTS}# Set analysis view to above for both setup and holdset_analysis_view-setup {TYPview} \-hold {TYPview}Floorplan I/O assignment file Specify placement of I/O pins on the IO box Read pin placement from file via Tclcommand:set init_io_file{ } Placement can be adjusted via Pin Place tool or editPincommand File format on next slideCOREIO assignment file format(globalsversion = 3io_order= clockwiseplace pins in this ordertotal_edge= 44 edges on the IO boxspace = 2global spacing of 2um between pins)(iopinstart pin definitions(leftpins on lieftside)(toppins on top side(pin name = "I[0]"pin namelayer = 3metal layer for connecting wirewidth = dimensionsdepth = = 2skip 2 positions to get away from cornerplace_status= fixed)(pinname = "I[1] layer = 3width = = fixed)Continue for other pins, including right and bottom sidesPower planning Specify power/ground net name(s) Tclcommandsset init_pwr_net{VDD} VDD net name(s)set init_gnd_net{VSS}GND net name(s) CPF (Common Power Format) file is optional Can be used for low-power Design and timing Useful for multiple power domains required TCL command.))

4 Set init_cpf_file{ }Analysis Configuration MMMC View Definition File Multi-Mode/Multi-Corner analysis Specify timing libraries for process corners Worst case and best case timing (min/max delays, etc.) Used to meet timing constraints and calculate delays If MMMC info not provided, Physical Design only Tclcommand:set init_mmmc_file{ } MMMC to be discussed laterFloorplanninga standard cell blockIO Box (pin locations)Core CellSpace for Power ringsChip floorplanhas modulesand I/O padsGNDrails(assume no hand-placed blocks)Specify floorplanSpecify by sizeor by coordinatesCore size aspect ratio Core utilization %leaves space for routingCore to IO boundaryleaves space for power TclCommandsetDrawViewfplan- display floorplan viewsetFPlanRowSpacingAndType$rowgap1flo orplan r 20 20 20 20 Coreto IOAspectRatio(H/W)Densityleft bottom right topCore-to-IO spacing Can also specify core and/or die & IO pad dimensions Defaults.

5 IO pins vs Pads,1stcell row flip from bottom up Initiate floorplanningand generate tracks1 every row2 every other rowFloorplan forModulo6 Aspect = 1(3 cell rows)Core-to-IOmargins = 20 coreIO boxWHMarginPower Planning:Add Power RingsAround core or I/O boxFor each side: Metal layer Metal width Spacing between wires Offset from boundary or center in channelPower Planning Specify configuration of power ringssetAddRingMode stacked_via_top_layerM3-stacked_via_bott om_layerM1addRing nets { VDD VSS } \-type core_rings\-around user_defined\-center 0 \-spacing $pspace\-width $pwidth\-offset $poffset\-threshold auto \-layer {bottom M1 top M1 right M2 left M2 }Around coreboundary1 to centerrings in channelMetal wire layersPower RingsGroundPowermodulo6coreM1M2 Power stripesOptional: Additional connections from power ringsto power/ground rails in the : addStripeAdd StripesToolBetween sets of stripesStripe wiresUse rings around coreSpace from core edges# Make Power Stripes.

6 This step is optional. # Check the stripe spacing (set-to-set-distance = $sspace) # and stripe offset (xleft-offset = $soffset)) addStripe-nets { VSS VDD } \-layer M2 \-width $swidth\-spacing $pspace\-xleft_offset$soffset\-set_to_se t_distance$sspace\-block_ring_top_layer_ limitM3 \-block_ring_bottom_layer_limitM1 \-padcore_ring_bottom_layer_limitM1 \-padcore_ring_top_layer_limitM3 \-stacked_via_top_layerM3 \-stacked_via_bottom_layerM1 \ \-snap_wire_center_to_gridGrid \ power stripes TclcommandLowest layer touse if objectencounteredMerge with core ringif this closePower stripesadded to ringsSpecial route VDD/VSS wires between rings and core power railsNets to be connectedJog & change metal layersto avoid obstaclesObjects to connectto powersroute connect {blockPinpadPinpadRingcorePinfloatingStr ipe} \-allowJoggingtrue \-allowLayerChangetrue \-blockPinuseLef\-targetViaLayerRange{M1 AM }Objects to connect to rings/stripesTo avoidDRC errorsTcl.

7 After SpecialRoutingVDDVSSPin Editor Form to adjust placementSelect pins and sidePin layer and geometryPin spacing pattern:space from Startspace from Center spread between coord sspread across side/edgespacing directionspacing amount (unless spread )Use Apply to experiment with options until editing Tclcommand# Pin placement sectioneditPin-side TOP \-layer M3 \-fixedPin1 \-spreadTypeCENTER \-spacing 4 \-pin { I[0] I[1] I[2] CLEARbarCLK }editPin-side BOTTOM \-layer M3 \-fixedPin1 \-spreadTypeRANGE \-start { 4 0} \-end {50 0} \-spreadDirectionCounterClockwise\-pin { Q[0] Q[1] Q[2] L_Cbar}Space by 4,begin in centerSpread out evenlybetween end points-side Top -spreadtypeCENTER spacing 4-side Bottom -spreadTypeRANGE start {4 0} end {50 0}-spreadDirectionCounterClockwisePin editingExampleTop pins spreadfrom center withspacing = 4 Bottom pins spread evenlybetween (x y)=(4,0) to (50,0)

8 Place standard cells setupsetPlaceMode timingDriventrue \-congEffortautoplaceDesignsetDrawViewpl aceOptional placeDesignswitches:-inPlaceOptor -prePlaceOpt(to view the cells)TclCommandsMode on next slidePlace Standard Cells Mode SetupsetPlaceMode-congEffortauto \ timingDriventrue \-ignoreScantrueAfterPlacingCellsDraw View place Timing analysis and optimization Ideally perform at three times during the Design flow Pre-CTS(clock tree synthesis) trial route after placing cells Post-CTS clock tree should improve timing Post-Route after completed routing timeDesign: create trial route, extract delays, analyze timing, generate reports (reg2reg, in2reg, reg2out) optDesign:resize gates, restructure netlist, add/delete buffers, swap pins, move instancesTiming reportssetAnalysisMode-analysisTypeonChi pVariation-skew true -clockPropagationsdcControltimeDesign preCTS idealClock numPaths50 prefix preCTS\ outDir${BASENAME}_reports/preCTS(or: postCTS, postRoute)Option for postRouteonlydesign-rule violationTiming optimizationsetAnalysisMode-analysisType onChipVariation-skew true -clockPropagationsdcControlsetOptMode yieldEffortnonesetOptMode effort highsetOptMode fixDRCtruesetOptMode fixFanoutLoadtruesetOptMode optimizeFFtruesetOptMode simplifyNetlistfalsesetOptMode allsetOptMode usefulSkewfalseoptDesign preCTS drv\ outDir${BASENAME}_reports/preCTSOptTimin gCommand for postRouteonlyClock tree synthesis (CTS)# Create the clock tree spec from the.

9 Sdcfile (from synthesis)createClockTreeSpec-output $ # Set -routeGuideto use routing guide during # Set routeClkNetto use NanoRouteduring # Perform clock tree synthesisclockDesign-outDir${BASENAME}_c lock_reportsclockbufferRemoved from GUI in current clock tree synthesisClock netchangedBuffer cell addedNanoRouteSetupCommand: globalDetailRouteDefaultoptionsusuallyOK From initial Innovusscript:# Set the name(s) of the filler cell(s) in the cell librarysetfillerCells[list FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64 ]After routing complete:# Add the filler cells setFillerMode-corePrefix${BASENAME}_FILL -core ${fillerCells}addFiller-cell $fillerCells-prefix ${BASENAME}FILL -markFixedAdd Filler CellsMenu:Place > Physical Cell > Add FillerAfter routingFiller cellsaddedDesign verification Verify connectivity, looking for: Antennas Opens Loops Unconnected pins Verify geometrywith data from LEF file: Widths Spacings Internal geometries of wires/objectsTCL:verifyConnectivity type regular error 50 warning 50 -report type special error 50 warning 50 -report allowSameCellViols noSameNet-noOverlap-report results# Export the DEF, v, spef, sdf, lef , and lib filesglobal dbgLefDefOutVersionset -netlist -routing $ ${BASENAME} defputs "----------Output ${BASENAME} saveNetlist[format "% " $BASENAME]puts "--------Save models for hierarchical flow------ saveModel-cts-sdf-spef-dir${BASENAME}_hi er_dataextractRC-outfile$ $ #delayCal-sdf$ idealclockwrite_sdf$ # Generate GDSII file from InnovusdatabaseSee next slideGenerate GDSII file from Innovusdatabase# Generate mask data for layout in GDSII formatsetStreamOutMode-snapToMGridtruest reamOut${BASENAME}.

10 Gds2 \-structureName${BASENAME} \-mode ALL \-outputMacros\-stripes 1 \-mapFile/class/ELEC6250/cmos8hp/ \-merge {/class/ELEC6250/cmos8hp/std_ }Standard cell layouts