Transcription of ASIC Physical Design Standard-Cell Design Flow
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ASIC Physical Design Standard-Cell Design Flow
ASIC Physical DesignStandard-Cell Design FlowUsing the Cadence InnovusDigital implementation SystemASIC Physical Design (Standard Cell)(can also do full custom layout)FloorplanChip/BlockPlace & RouteStd. CellsComponent-Level Verilog NetlistIC Mask DataDesign RuleCheckStd. CellLayoutsCadence Innovus Digital implementation SystemADiT/Eldo Simulation ModelBackannotateSchematicGenerateMask DataLayout RulesProcess DataLibrariesCalibreCalibreCalibreNetlis t-to-layoutdesign flowSynopsys JupiterXT Cadence SOC Innovus InnovusDigital implementation (EDI) System GUIEDI Design flowFloorplan ( flat ) through implementationDesign Import (specify input files)File > Design ImportGate-level netlist Verilog file(s) Physical data (LEF)Technology CellsIO pin planningPower planningTiming data andconstraintsExecutes init_designcommand to load files Verilog gate-level netlist(s) Gates from the standard cell library Design can be hierarchical or flat Tclcommands.
Implementation (EDI) System GUI. EDI design flow Floorplan (“flat”) through implementation. Design Import (specify input files) File > Design Import. Gate-level netlist Verilog file(s) Physical data (LEF) Technology Cells. IO pin planning. Power planning. Timing data and. constraints.
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