AT24C512C rev B Data Sheet - Microchip Technology

1 AT24C512C I C-Compatible (Two-Wire)Serial EEPROM 512 kbit (65,536 x 8)Features Low-Voltage and Standard-Voltage Operation: VCC = to VCC = to Internally Organized as 65,536 x 8 (512K) Industrial Temperature Range: -40 C to +85 C I2C-Compatible (Two-Wire) Serial Interface: 100 kHz Standard mode, to 400 kHz Fast mode, to 1 MHz Fast Mode Plus (FM+), to Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol Write-Protect Pin for Full Array Hardware Data Protection Ultra Low Active Current (3 mA maximum) and Standby Current (6 A maximum) 128-Byte Page Write Mode: Partial page writes allowed Random and Sequential Read Modes Self-Timed Write Cycle within 5 ms Maximum ESD Protection > 4,000V High Reliability: Endurance: 1,000,000 write cycles Data retention: 100 years Green Package Options (Lead-free/Halide-free/RoHS compliant) Die Sale Options: Wafer Form and Tape and Reel AvailablePackages 8-Lead SOIC, 8-Lead SOIJ, 8-Lead TSSOP, 8-Pad UDFN, 8-Ball WLCSP and 8-Ball VFBGA 2020 Microchip Technology Inc.

2 DatasheetDS20006161B-page 1 Table of Types (not to scale).. Address Inputs (A0, A1, A2).. Data (SDA).. Clock (SCL).. (WP).. Power Configuration Using Two-Wire Serial EEPROMs .. Maximum and AC Operating Operation and and Data Transition and Stop and Cycle Address Default Condition from AT24C512C 2020 Microchip Technology Inc. DatasheetDS20006161B-page Marking 37 The Microchip Change Notification 38 Product Identification Devices Code Protection 40 Quality Management 41 Worldwide Sales and AT24C512C 2020 Microchip Technology Inc. DatasheetDS20006161B-page 31. Package Types (not to scale)8-Lead SOIC/SOIJ/TSSOP(Top View)A012348765A1A2 GNDVCCWPSCLSDA12348765A0A1A2 GNDVCCWPSCLSDA8-Ball VFBGA(Top View)A0A1A2 GNDVCCWPSCLSDA8-Pad UDFN(Top View)123487658-Ball WLCSP(Top View)SDAA2 VCCWPSCLA1 GNDA0 AT24C512 CPackage Types (not to scale) 2020 Microchip Technology Inc.

3 DatasheetDS20006161B-page 42. Pin DescriptionsThe descriptions of the pins are listed in Table 2-1. Pin Function TableName8 Lead SOIC8 Lead SOIJ8 Lead TSSOP8 PadUDFN(1)8 Ball VFBGA8-BallWLCSPF unctionA0(2)11111A5 Device Address InputA1(2)22222B4 Device Address InputA2(2)33333C3 Device Address InputGND44444C5 GroundSDA55555C1 Serial DataSCL66666B2 Serial ClockWP(2)77777A3 Write-ProtectVCC88888A1 Device Power SupplyNote: 1. The exposed pad on this package can be connected to GND or left If the A0, A1, A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in awide variety of application environments, the pull down mechanism is intentionally designed to be somewhatstrong. Once these pins are biased above the CMOS input buffer s trip point (~ x VCC), the pull downmechanism disengages. Microchip recommends connecting these pins to a known state whenever Device Address Inputs (A0, A1, A2)The A0, A1 and A2 pins are device address inputs that are hard-wired (directly to GND or to VCC) for compatibilitywith other two-wire Serial EEPROM devices.

4 When the pins are hard-wired, as many as eight devices may beaddressed on a single bus system. A device is selected when a corresponding hardware and software match is these pins are left floating, the A0, A1 and A2 pins will be internally pulled down to GND. However, due tocapacitive coupling that may appear in customer applications, Microchip recommends always connecting the addresspins to a known state. When using a pull up resistor, Microchip recommends using 10 k or GroundThe ground reference for the power supply. GND should be connected to the system Serial Data (SDA)The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. TheSDA pin must be pulled high using an external pull-up resistor (not to exceed 10 k in value) and may be wire-ORedwith any number of other open-drain or open-collector pins from other devices on the same Serial Clock (SCL)The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device.

5 Commandand input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDApin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle orpulled high using an external pull-up resistor. AT24C512 CPin Descriptions 2020 Microchip Technology Inc. DatasheetDS20006161B-page Write-Protect (WP)The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connecteddirectly to VCC, all write operations to the protected memory are the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling thatmay appear in customer applications, Microchip recommends always connecting the WP pin to a known state. Whenusing a pull up resistor, Microchip recommends using 10 k or 2-2. Write-ProtectWP Pin StatusPart of the Array ProtectedAt VCCFull ArrayAt GNDN ormal Write Device Power SupplyThe VCC pin is used to supply the source voltage to the device.

6 Operations at invalid VCC voltages may producespurious results and should not be attempted. AT24C512 CPin Descriptions 2020 Microchip Technology Inc. DatasheetDS20006161B-page 63. DescriptionThe AT24C512C provides 524,288 bits of Serial Electrically Erasable and Programmable Read-Only Memory(EEPROM) organized as 65,536 words of 8 bits each. The device s cascading feature allows up to eight devices toshare a common two wire bus. The device is optimized for use in many industrial and commercial applications wherelow power and low voltage operation are essential. The devices are available in space saving 8 lead SOIC, 8 leadSOIJ, 8 lead TSSOP, 8 pad UDFN, 8-ball WLCSP and 8 ball VFBGA packages. All packages operate from or to System Configuration Using Two-Wire Serial EEPROMsI2C Bus Master:MicrocontrollerSlave 0AT24 CXXXVCCWPSDASCLA0A1A2 GNDVCCGNDSCLSDAWPRPUP(max) = tR(max) x CLRPUP(min) = VCC - VOL(max)IOLS lave 1AT24 CXXXVCCWPSDASCLA0A1A2 GNDS lave 7AT24 CXXXVCCWPSDASCLA0A1A2 GNDVCC AT24C512 CDescription 2020 Microchip Technology Inc.

7 DatasheetDS20006161B-page Block Diagram1 pageStartStopDetectorGNDA2 MemorySystem ControlModuleHigh-VoltageGeneration CircuitData & ACK Input/Output ControlAddress Registerand CounterWrite Protection ControlDOUTDINH ardwareAddressComparatorVCCWPSCLSDAP ower-on ResetGeneratorEEPROM ArrayColumn DecoderRow DecoderData RegisterA1A0 AT24C512 CDescription 2020 Microchip Technology Inc. DatasheetDS20006161B-page 84. Electrical Absolute Maximum RatingsTemperature under bias-55 C to +125 CStorage temperature-65 C to +150 on any pin with respect to to + output mAESD protection> 4 kVNote: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the is a stress rating only and functional operation of the device at these or any other conditions above thoseindicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect device DC and AC Operating RangeTable 4-1.

8 DC and AC Operating RangeAT24C512 COperating Temperature (Case)Industrial Temperature Range-40 C to +85 CVCC Power SupplyLow-Voltage to to DC CharacteristicsTable 4-2. DC CharacteristicsParameterSymbolMinimumTyp ical(1)MaximumUnitsTest ConditionsSupply CurrentICC1 = , Read at 400 kHz = , Write at 400 kHzICC2 = , Read at 400 kHz = , Write at 400 kHzStandby CurrentISB1 AVCC = , VIN = VCC or GND AVCC = , VIN = VCC or GNDISB2 AVCC = , VIN = VCC or VSS AVCC = , VIN = VCC or VSSI nput LeakageCurrentILI AVIN = VCC or GND; VCC = AT24C512 CElectrical Characteristics 2020 Microchip Technology Inc. DatasheetDS20006161B-page (1)MaximumUnitsTest ConditionsOutput LeakageCurrentILO AVOUT = VCC or GND; VCC = Low VCC x 2 Input High LevelVIHVCC x VCC + 2 Output Low LevelVOL1 = , IOL = mAOutput Low LevelVOL2 = , IOL = mANote: 1. Typical values characterized at TA = +25 C unless otherwise This parameter is characterized but is not 100% tested in AC CharacteristicsTable 4-3.

9 AC Characteristics(1)ParameterSymbolFast ModeFast Mode PlusUnitsVCC = to = to Frequency, SCLfSCL 400 1000kHzClock Pulse Width LowtLOW1300 500 nsClock Pulse Width HightHIGH600 400 nsNoise Suppression Time(2)tI 50 50nsClock Low to Data Out ValidtAA5090050450nsBus Free Time between Stop andStart(2)tBUF1300 500 nsStart Hold 250 nsStart Set up 250 nsData In Hold 0 nsData In Set up 100 nsInputs Rise Time(2)tR 300 300nsInputs Fall Time(2)tF 300 100nsStop Set-up 250 nsData Out Hold TimetDH50 50 nsWrite Cycle TimetWR 5 5ms AT24C512 CElectrical Characteristics 2020 Microchip Technology Inc. DatasheetDS20006161B-page 10 Note: 1. AC measurement conditions: CL = 100 pF RPUP (SDA bus line pull-up resistor to VCC): k (1000 kHz), 4 k (400 kHz), 10 k (100 kHz) Input pulse voltages: VCC to VCC Input rise and fall times: 50 ns Input and output timing reference voltages: x VCC2. This parameter is ensured by characterization and is not 100% 4-1.

10 Bus TimingSCLSDA InSDA Electrical Power-Up Requirements and Reset BehaviorDuring a power-up sequence, the VCC supplied to the AT24C512C should monotonically rise from GND to theminimum VCC level, as specified in Table 4-1, with a slew rate no faster than V/ Device ResetTo prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, theAT24C512C includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commandsuntil the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into system designer must ensure the instructions are not sent to the device until the VCC supply has reached astable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to theminimum VCC level, the bus master must wait at least tPUP before sending the first command to the device.