Atmel | SMART AT91RM9200 Datasheet

1 Atmel -1768J-ATARM- AT91RM9200 -Datasheet_0 3-Mar-16 DescriptionThe Atmel | SMART AT91RM9200 is a complete system-on-chip built around theARM920T ARM Thumb processor. It incorporates a rich set of system andapplication peripherals and standard interfaces in order to provide a single-chipsolution for a wide range of compute-intensive applications that require maximumfunctionality at minimum power consumption at lowest AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and alow-latency External Bus Interface (EBI) for seamless connection to whateverconfiguration of off-chip memories and memory-mapped peripherals is requiredby the application. The EBI incorporates controllers for synchronous DRAM(SDRAM), Burst Flash and Static memories and features specific circuitryfacilitating the interface for NAND Flash/SmartMedia and Advanced Interrupt Controller (AIC) enhances the interrupt handlingperformance of the ARM920T processor by providing multiple vectored, prioritizedinterrupt sources and reducing the time taken to transfer to an interrupt Peripheral DMA Controller (PDC) provides DMA channels for all the serialperipherals, enabling them to transfer data to or from on- and off-chip memorieswithout processor intervention.

2 This reduces the processor overhead whendealing with transfers of continuous data streams. The AT91RM9200 benefitsfrom a generation of PDC which includes dual pointers that significantly simplifybuffer set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lineswith general-purpose data I/Os for maximum flexibility in device configuration. Aninput change interrupt, open drain capability and programmable pull-up resistor isincluded on each line. The Power Management Controller (PMC) keeps system power consumption to aminimum by selectively enabling/disabling the processor and various peripheralsunder software control. It uses an enhanced clock generator to provide a selectionof clock signals including a slow clock (32 kHz) to optimize power consumptionand performance at all AT91RM9200 integrates a wide range of standard interfaces including Full Speed Host and Device and Ethernet 10/100 Base-T Media AccessController (MAC), which provides connection to an extensive range of externalperipheral devices and a widely used networking layer.

3 In addition, it provides arich set of peripherals that operate in accordance with several industry standards,such as those used in audio, telecommunication, Flash Card, infrared and SmartCard | SMART ARM-based Embedded MPUDATASHEETAT91RM9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-162To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features includingJTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real-time trace. This enables thedevelopment and debug of all applications, especially those with real-time Incorporates ARM920T ARM Thumb Processor 200 MIPS at 180 MHz, Memory Management Unit 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer In-circuit Emulator including Debug Communication Channel Mid-level Implementation Embedded Trace Macrocell (256-ball LFBGA Package only) Low Power: On VDDCORE mA in Normal Mode, 520 A in Standby Mode Additional Embedded Memories 16 Kbytes of SRAM and 128 Kbytes of ROM External Bus Interface (EBI) Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash and NAND Flash/SmartMedia System Peripherals for Enhanced Performance.

4 Enhanced Clock Generator and Power Management Controller Two On-chip Oscillators with Two PLLs Very Slow Clock Operating Mode and Software Power Optimization Capabilities Four Programmable External Clock Signals System Timer Including Periodic Interrupt, Watchdog and Second Counter Real-time Clock with Alarm Interrupt Debug Unit, Two-wire UART and Support for Debug Communication Channel Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected Seven External Interrupt Sources and One Fast Interrupt Source Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain Capability on Each Line 20-channel Peripheral DMA Controller (PDC) Ethernet MAC 10/100 Base-T Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit USB Full Speed (12 Mbits per second) Host Double Port Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package) Integrated FIFOs and Dedicated DMA Channels USB Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Multimedia Card Interface (MCI) Automatic Protocol Control and Fast Automatic Data Transfers MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards Three Synchronous Serial Controllers (SSC) Independent Clock and Frame Sync Signals for Each Receiver and Transmitter I2S Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer3AT91RM9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-16 Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

5 Support for ISO7816 T0/T1 SMART Card Hardware Handshaking RS485 Support, IrDA Up To 115 Kbps Full Modem Control Lines on USART1 Master/Slave Serial Peripheral Interface (SPI) 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects Two 3-channel, 16-bit Timer/Counters (TC) Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) Master Mode Support, All 2-wire Atmel EEPROMs Supported IEEE JTAG Boundary Scan on All Digital Pins Power Supplies to for VDDCORE, VDDOSC and VDDPLL to for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os) Packages 208-pin Green PQFP 256-ball RoHS-compliant LFBGAAT91RM9200 [ Datasheet ] DiagramBold arrows () indicate master-to-slave dependency. Figure Block DiagramARM920T CoreJTAGScanICEAICFast SRAM16 KbytesPIOPLLBPLLAOSCPMCS ystemTimerOSCRTCEBIPIOA/PIOB/PIOC/PIODC ontrollerDBGUMCIUSART0 USART1 USART2 USART3 SPISSC0 SSC1 SSC2 Timer CounterTC0TC1TC2 Timer CounterTC3TC4TC5 TWIPIOPIOD0 D15A0/NBS0A1/NBS2/NWR2A2 A15/A18 A22A16/BA0A17/BA1 NCS0/BFCSNCS1/SDCSNCS3/SMCSNRD/NOE/CFOEN WR0/NWE/CFWENWR1/NBS1/CFIORNWR3/NBS3/CFI OWSDCKSDCKERAS-CASSDWESDA10 BFRDY/SMOEBFCKBFAVDBFBAA/SMWEBFOEBFWEA23 A24 NWAITNCS5/CFCE1D16 D31TF0TK0TD0RD0RK0RF0TF1TK1TD1RD1RK1RF1T F2TK2TD2RD2RK2RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TWDTWCKJTAGSELTDITDOTMSTCKNTRSTFIQIRQ0 IRQ6 PCK0 PCK3 PLLRCBPLLRCAXINXOUTXIN32 XOUT32 DDMDDPMCCKMCCDAMCDA0 MCDA3 MCCDBRXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 DCD1RI1 RXD2 TXD2 SCK2 RTS2 CTS2 RXD3 TXD3 SCK3 RTS3 CTS3 NPCS0 NPCS1 NPCS2 NPCS3 MISOMOSISPCKMCDB0 MCDB3 HDMAHDPBHDPAHDMBDRXDDTXDE thernet MAC

6 10/100 ETXCK-ERXCK-EREFCKETXEN-ETXERECRS-ECOLER XER-ERXDVERX0 ERX3 ETX0 ETX3 EMDCSDRAMC ontrollerBurstFlashControllerStaticMemor yControllerPIOI nstruction Cache16 KbytesData Cache16 KbytesMMUEMDIODMAFIFODMAFIFOUSB HostFIFOUSB DeviceTransceiverPIOPIOPIOR esetandTestTST0 TST1 NRSTAPBFast ROM128 KbytesBMSNCS2A25/CFRNWNCS4/CFCSM isalignmentDetectorAddressDecoderAbortSt atusNCS6/CFCE2 TransceiverNCS7 MemoryControllerBusArbiterPeripheralBrid gePeripheralDMAC ontrollerEF100 ETMTSYNCTCLKTPS0 TPS2 TPK0 TPK15 CompactFlashNAND FlashSmartMediaPDCPDCPDCPDCPDCPDCPDCPDCP DCPDCPDCPDC5AT91RM9200 [ Datasheet ] DescriptionTable Description by PeripheralPin NameFunctionTypeActiveLevelCommentsPower VDDIOMM emory I/O Lines Power VVDDIOPP eripheral I/O Lines Power VVDDPLLO scillator and PLL Power VVDDCORECore Chip Power VVDDOSCO scillator Power VGNDG roundGroundGNDPLLPLL GroundGroundGNDOSCO scillator GroundGroundClocks, Oscillators and PLLsXINMain Crystal InputInputXOUTMain Crystal OutputOutputXIN3232 kHz Crystal InputInputXOUT3232 kHz Crystal OutputOutputPLLRCAPLL A Filter InputPLLRCBPLL B FilterInputPCK0 PCK3 Programmable Clock OutputOutputICE and JTAGTCKTest ClockInputSchmitt triggerTDITest Data InInputInternal Pull-up, Schmitt triggerTDOTest Data OutOutputTri-stateTMSTest Mode SelectInputInternal Pull-up, Schmitt triggerNTRSTTest Reset SignalInputLowInternal Pull-up.

7 Schmitt triggerJTAGSELJTAG SelectionInputSchmitt triggerETM TSYNCT race Synchronization SignalOutputTCLKT race ClockOutputTPS0 TPS2 Trace ARM Pipeline StatusOutputTPK0 TPK15 Trace Packet PortOutputReset/TestNRSTM icroprocessor ResetInputLowNo on-chip pull-up, Schmitt triggerTST0 TST1 Test Mode SelectInputMust be tied low for normal operation, Schmitt triggerMemory ControllerBMSBoot Mode SelectInputAT91RM9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-166 Debug UnitDRXDD ebug Receive DataInputDebug Receive DataDTXDD ebug Transmit DataOutputDebug Transmit DataAICIRQ0 IRQ6 External Interrupt InputsInputFIQFast Interrupt InputInputPIOPA0 PA31 Parallel IO Controller AI/OPulled-up input at resetPB0 PB29 Parallel IO Controller BI/OPulled-up input at resetPC0 PC31 Parallel IO Controller CI/OPulled-up input at resetPD0 PD27 Parallel IO Controller DI/OPulled-up input at resetEBID0 D31 Data BusI/OPulled-up input at resetA0 A25 Address BusOutput0 at resetSMCNCS0 NCS7 Chip Select LinesOutputLow1 at resetNWR0 NWR3 Write SignalOutputLow1 at resetNOEO utput EnableOutputLow1 at resetNRDRead SignalOutputLow1 at resetNUBU pper Byte SelectOutputLow1 at resetNLBL ower Byte SelectOutputLow1 at resetNWEW rite EnableOutputLow1 at resetNWAITWait SignalInputLowNBS0 NBS3 Byte Mask SignalOutputLow1 at resetEBI for CompactFlash SupportCFCE1 CFCE2 CompactFlash Chip

8 EnableOutputLowCFOEC ompactFlash Output EnableOutputLowCFWEC ompactFlash Write EnableOutputLowCFIORC ompactFlash IO Read OutputLowCFIOWC ompactFlash IO WriteOutputLowCFRNWC ompactFlash Read Not WriteOutputCFCSC ompactFlash Chip SelectOutputLowEBI for NAND Flash/SmartMedia SupportSMCSNAND Flash/SmartMedia Chip SelectOutputLowSMOENAND Flash/SmartMedia Output EnableOutputLowSMWENAND Flash/SmartMedia Write EnableOutputLowTable Description by Peripheral (Continued)Pin NameFunctionTypeActiveLevelComments7AT91 RM9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-16 SDRAM ControllerSDCKSDRAM ClockOutputSDCKESDRAM Clock EnableOutputHighSDCSSDRAM Controller Chip SelectOutputLowBA0 BA1 Bank SelectOutputSDWESDRAM Write EnableOutputLowRAS - CASRow and Column SignalOutputLowSDA10 SDRAM Address 10 LineOutputBurst Flash ControllerBFCKB urst Flash ClockOutputBFCSB urst Flash Chip SelectOutputLowBFAVDB urst Flash Address ValidOutputLowBFBAAB urst Flash Address AdvanceOutputLowBFOEB urst Flash Output EnableOutputLowBFRDYB urst Flash Ready InputHighBFWEB urst Flash Write EnableOutputLowMultimedia Card InterfaceMCCKM ultimedia Card ClockOutputMCCDAM ultimedia Card A CommandI/OMCDA0 MCDA3 Multimedia Card A DataI/OMCCDBM ultimedia Card B CommandI/OMCDB0 MCDB3 Multimedia Card B DataI/OUSARTSCK0 SCK3 Serial ClockI/OTXD0 TXD3 Transmit DataOutputRXD0 RXD3 Receive DataInputRTS0 RTS3 Ready To SendOutputCTS0 CTS3 Clear To Send InputDSR1 Data Set ReadyInputDTR1 Data Terminal

9 ReadyOutputDCD1 Data Carrier DetectInputRI1 Ring IndicatorInputUSB Device PortDDMUSB Device Port Data - AnalogDDPUSB Device Port Data +AnalogTable Description by Peripheral (Continued)Pin NameFunctionTypeActiveLevelCommentsAT91R M9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-168 USB Host PortHDMAUSB Host Port A Data - AnalogHDPAUSB Host Port A Data +AnalogHDMBUSB Host Port B Data - AnalogHDPBUSB Host Port B Data +AnalogEthernet MACEREFCKR eference ClockInputRMII only ETXCKT ransmit ClockInputMII onlyERXCKR eceive ClockInputMII onlyETXENT ransmit EnableOutputETX0 ETX3 Transmit DataOutputETX0 ETX1 only in RMIIETXERT ransmit Coding ErrorOutputMII onlyERXDVR eceive Data ValidInputMII onlyECRSDVC arrier Sense and Data ValidInputRMII onlyERX0 ERX3 Receive DataInputERX0 ERX1 only in RMIIERXERR eceive ErrorInputECRSC arrier SenseInputMII onlyECOLC ollision DetectedInputMII onlyEMDCM anagement Data ClockOutputEMDIOM anagement Data Input/OutputI/OEF100 Force 100 Mbit/sOutputHighRMII onlySynchronous Serial ControllerTD0 TD2 Transmit DataOutputRD0 RD2 Receive DataInputTK0 TK2 Transmit ClockI/ORK0 RK2 Receive ClockI/OTF0 TF2 Transmit Frame SyncI/ORF0 RF2 Receive Frame

10 SyncI/OTimer/CounterTCLK0 TCLK5 External Clock InputInputTIOA0 TIOA5I/O Line AI/OTIOB0 TIOB5I/O Line BI/OSPIMISOM aster In Slave OutI/OMOSIM aster Out Slave InI/OSPCKSPI Serial ClockI/ONPCS0 SPI Peripheral Chip Select 0I/OLowNPCS1 NPCS3 SPI Peripheral Chip SelectOutputLowTable Description by Peripheral (Continued)Pin NameFunctionTypeActiveLevelComments9AT91 RM9200 [ Datasheet ] Atmel -1768J-ATARM- AT91RM9200 - Datasheet_03-Mar-16 Two-Wire InterfaceTWDTwo-wire Serial Data I/OTWCKTwo-wire Serial ClockI/OTable Description by Peripheral (Continued)Pin NameFunctionTypeActiveLevelCommentsAT91R M9200 [ Datasheet ] and PinoutThe AT91RM9200 is available in two packages: 208-pin PQFP, x mm, mm pitch 256-ball LFBGA, 15 x 15 mm, mm ball pitchThe product features of the 256-ball LFBGA package are extended compared to the 208-lead PQFP package. Thefeatures that are available only with the 256-ball LFBGA package are: Parallel I/O Controller D ETM port with outputs multiplexed on the PIO Controller D a second USB Host transceiver, opening the Hub capabilities of the embedded USB PQFP Package OutlineFigure 3-1 shows the orientation of the 208-pin PQFP detailed mechanical description is given in Section 38.