ATPL230A - Microchip Technology

1 Atmel-43053J- ATPL230A -Datasheet_22-Sep-1 6 DescriptionATPL230A is a power line communications base band modem, compliant with thePHY layer of PRIME (Power Line Intelligent Metering Evolution) is an open standard Technology used for Smart Grid applications like SmartMetering, Industrial Lighting and Automation, Home Automation, Street Lighting,Solar Energy and PHEV Charging Stations. ATPL230A PRIME device includes enhanced features such as additional robustmodes and frequency band extension. ATPL230A is able to operate in indepen-dently selectable transmission bands up to 472 kHz, achieving baud rates rangingfrom kbps up to kbps. ATPL230A has been conceived to be bundled with an external Atmel MCU orMPU. Atmel provides a PRIME PHY layer library which is used by the externalMCU/MPU to take control of ATPL230A PHY layer Series Power Line Communications DeviceDATASHEETATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 Modem Power Line Carrier Modem for 50 Hz and 60 Hz mains 97-carriers OFDM PRIME compliant DBPSK, DQPSK, D8 PSK modulation schemes available Additional enhanced modes available: DBPSK Robust and DQPSK Robust Eight selectable channels between 42kHz and 472kHz available.

2 Only one channel can be active at atime Baud rate Selectable: to kbps Four dedicated buffers for transmission/reception Up to dB Vrms injected signal against PRIME load Up to dB of dynamic range in PRIME networks Automatic Gain Control and continuous amplitude tracking in signal reception Class D switching power amplifier control Integrated LDO regulator to supply analog functions Medium Access Control co-processor features Viterbi soft decoding and PRIME CRC calculation 128-bit AES encryption Channel sensing and collision pre-detection41,99288,86796, ,242206,055252,930260,742307,617315,4303 62,305370,117416,992424,805471,680 CENELEC A - BCDARIBFCCCHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8f (kHz) 3 ATPL230A [DATASHEET] DiagramFigure 2-1. ATPL230A Functional Block DiagramADCVIMAVRPVRMVRCVIPAEMIT(0:5)TXRX 0 EMIT(6:11)TXRX1 EMITER_CTRLAGC_CTRLAGC(0:5)ZERO CROSS DETECTORVZ CROSSBERCDRSSIPHYCONTROLCLOCK & RESET INTERFACEARSTPLL INITCLKEACLKEBSRSTPOWER MANAGEMENTVDDPLL GNDVDDIN VDDOUT VDDIOVDDOUT ANCLKOUTT ransmission ChainVDDIN ANATPL230 APHY_COREBUF_RX1 TXDRV0 Recep on ChainAGNDSPI BRIDGE MOSIEINTMISOSCKCSTXDRV1 BUF_RX0 BUF_RX2 BUF_TX1 BUF_TX2 BUF_TX3 CINREVMCRCAESBUF_RX3 BUF_TX0 ATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 DescriptionTable Description ListSignal NameFunctionTypeActive LevelVoltage referenceCommentsPower digital supply.

3 Digital power supply mustbe decoupled by external to Digital LDO input to Analog LDO input to Analog LDO output. A capacitor in therange F - 10 F must be connected toeach Digital LDO output. A capacitor in therange F - 10 F must be connected toeach PLL supply. It must be decoupled by a100nF external capacitor, and connected toVDDOUT through a filter (Cut off frequency:25kHz) (1)Digital GroundPowerAGND(1)Analog GroundPowerClocks, Oscillators and PLLsCLKEA(2)External Clock Oscillator CLKEA must be connected to one terminalof a crystal (when a crystal is being used) orused as input for external clock signalInputVDDIOCLKEB(2)External Clock Oscillator CLKEB must be connected to one terminalof a crystal (when a crystal is being used) ormust be floating when an external clocksignal is connected through CLKEAI/OVDDIOCLKOUT10 MHz External Clock OutputOutputVDDIOR eset/TestARSTA synchronous ResetInputLowVDDIOI nternal pull up(3) SRSTS ynchronous ResetInputLowVDDIOI nternal pull up(3) PLL INITPLL Initialization SignalInputLowVDDIOI nternal pull up(3) PPLC (PRIME Power Line Communications) TransceiverEMIT [0:11](4)PLC Tri-state Transmission portsOutputVDDIOAGC [0.]

4 5]Automatic Gain Control: These digital tri-state outputs are managedby AGC hardware logic to drive externalcircuitry when input signal attenuation isneededOutputVDDIO 5 ATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 Notes: 1. Separate pins are provided for GND and AGND grounds. Layout considerations should be taken into account toreduce interference. Ground pins should be connected as shortly as possible to the system ground plane. Formore details about EMC Considerations, please refer to AVR040 application The crystal should be located as close as possible to CLKEA and CLKEB pins. See Table 10-7 on page See Table 10-5 on page Different configurations allowed depending on external topology and net Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should betaken into account in the circuitry design.

5 Please refer to the Reference Design for further Front-End Transmission/Reception forTXDRV0 This digital output is used to modifyexternal coupling behavior inTransmission/Reception. The suitablevalue depends on the external circuitryconfiguration. The polarity of this pin can beinverted by Front-End Transmission/Reception forTXDRV1 This digital output is used to modifyexternal coupling behavior inTransmission/Reception. The suitablevalue depends on the external circuitryconfiguration. The polarity of this pin can beinverted by CROSS(5)Mains Zero-Cross Detection Signal: This input detects the zero-crossing of themains voltageInputVDDIOI nternal pull down(3)VIMAN egative Differential Voltage InputInputVDDOUT ANVIPAP ositive Differential Voltage InputInputVDDOUT ANVRPI nternal Reference Plus Voltage.

6 Connect anexternal decoupling capacitor between VRPand VRM (1nF - 100nF)OutputVDDOUT ANVRMI nternal Reference Minus Voltage. Connectan external decoupling capacitor betweenVRP and VRM (1nF - 100nF)OutputVDDOUT ANVRCC ommon-mode Voltage. Bypass to analogground with an external decoupling capacitor(100pF - 1nF) OutputVDDOUT ANSerial Peripheral Interface - SPI CSSPI CS SPI bridge Slave SelectInputLowVDDIOI nternal pull up(3) SCKSPI SCK SPI bridge Clock signalInputVDDIOI nternal pull up(3) MOSISPI MOSI SPI bridge Master Out Slave InInputVDDIOI nternal pull up(3) MISOSPI MISO SPI bridge Master In Slave OutOutputVDDIOEINTPHY Layer External InterruptOutputLowVDDIOT able Description ListSignal NameFunctionTypeActive LevelVoltage referenceCommentsATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 and LQFP Package OutlineFigure 4-1.

7 Orientation of the 80-Lead LQFP LQFP Pinout120214041606180 Table - Lead LQFP Pinout1NC21 VDDIO41 GND61 GND2NC22NC42 EMIT862 AGND3NC23 CLKOUT43 EMIT963 VDDOUT AN4 ARST24CS44 EMIT1064 VIMA5 PLL INIT25 SCK45 EMIT1165 VIPA6 GND26 MOSI46 VDDIO66 VDDOUT AN7 CLKEA27 MISO47 GND67 AGND8 GND28 VDDIO48 VDDOUT68 VRP9 CLKEB29 GND49 TXRX069 VRM10 VDDIO30 EMIT050 TXRX170 VRC11 GND31 EMIT151 GND71 VDDIN AN12 VDDPLL32 EMIT252 AGC272 AGND13 GND33 EMIT353 AGC573 AGND14 VDDIN34 VDDIO54 AGC174 VDDIN AN15 VDDIN35 GND55 AGC475 GND16 GND36 EMIT456 AGC076 VDDIO17 VDDOUT37 EMIT557 AGC377VZ CROSS18 GND38 EMIT658 VDDIO78NC19NC39 EMIT759 GND79NC20 SRST40 VDDIO60 EINT80NC 7 ATPL230A [DATASHEET] coupling circuitry descriptionAtmel PLC coupling reference designs have been designed to achieve high performance, low cost and these values on mind, Atmel has developed a set of PLC couplings covering frequencies up to 472 kHzcompliant with different applicable PLC Technology is purely digital and does not require external DAC/ADC, thus simplifying the external requiredcircuitry.

8 Generally Atmel PLC coupling reference designs make use of few passive components plus a Class Damplification stage for PLC coupling reference designs are generally composed by the same sub-circuits: Transmission Stage Reception Stage Filtering Stage Coupling StageFigure 5-1. PLC coupling block diagramA particular reference design can contain more than one sub-circuit of the same kind ( : two transmission stages). Transmission StageThe transmission stage adapts the EMIT signals and amplifies them if required. It can be composed by: Driver: A group of resistors which adapt the EMIT signals to either control the Class-D amplifier or to be filteredby the next stage. Amplifier: If required, a Class-D amplifier which generates a square waveform from 0 to VDD is included. Bias and protection: A couple of resistors and a couple of Schottky barrier diodes provide a DC component andprovide protection from received stage shall be always followed by a filtering MAINSRECEPTION STAGETRANSMISSION STAGECOUPLING STAGEATPL230 AVDDFILTERING STAGEATPL230A [DATASHEET]Atmel-43053J- ATPL230A -Datashe et_22-Sep-16 Filtering StageThe filtering stage is composed by band-pass filters which have been designed to achieve high performance in fielddeployments complying at the same time with the proper normative and in-band flat response filtering stage does not distort the injected signal, reduces spurious emission to the limitsset by the corresponding regulation and blocks potential interferences from other transmission filtering stage has three aims.

9 Band-pass filtering of high frequency components of the square waveform generated by the transmission stage Adapt Input/Output impedances for optimal reception/transmission. This is controlled by TXRX signals In some cases, Band-pass filtering for received signalsWhen the system is intended to be connected to a physical channel with high voltage or which is not electricallyreferenced to the same point then the filtering stage must be always followed by a coupling Coupling StageThe coupling stage blocks the DC component of the line to/from which the signal is injected/received ( : 50/60 Hz ofthe mains). This is carried out by a high voltage stage could also electrically isolate the coupling circuitry from the external world by means of a 1 Reception StageThe reception stage adapts the received analog signal to be properly captured by the ATPL230A internal receptionchain.

10 Reception circuit is independent of the PLC channel which is being used. It basically consists of: Anti aliasing filter (RC Filter) Automatic Gain Control (AGC) circuit Driver of the internal ADCThe AGC circuit avoids distortion on the received signal that may arise when the input signal is high enough topolarize the protective diodes in direct driver to the internal ADC comprises a couple of resistors and a couple of capacitors. This driver provides a DCcomponent and adapts the received signal to be properly converted by the internal reception chain. 9 ATPL230A [DATASHEET] Generic PLC CouplingPlease consider that this is a generic PLC Coupling design for a particular application please refer to Atmel doc43052 PLC Coupling Reference Designs .Figure 5-2. PLC Coupling block diagram reference designsAtmel provides PLC coupling reference designs for different applications and frequency bands up to 500 kHz.