AVR® Instruction Set Manual - Microchip Technology

1 AVR Instruction Set Manual AVR Instruction Set ManualIntroductionThis Manual gives an overview and explanation of every Instruction available for 8-bit AVR devices. Each instructionhas its own section containing functional description, it s opcode, and syntax, the end state of the status register, andcycle Manual also contains an explanation of the different addressing modes used by AVR devices and an appendixlisting all modern AVR devices and what Instruction it has available. 2021 Microchip Technology Inc. ManualDS40002198B-page 1 Table of Set Registers Located in the I/O , RAMPY, and Program and Data Addressing Direct, Single Register Direct - Two Registers, Rd and Indirect with Indirect with Indirect with Memory Constant Addressing using the LPM, ELPM, and SPM Memory with Post-increment using the LPM Z+ and ELPM Z+ Program Memory Program Addressing, JMP and Program Addressing, IJMP and Indirect Program Addressing, EIJMP and Program Addressing, RJMP and Branch Set Add with Add without Add Immediate to Logical Logical AND with Arithmetic Shift Bit Clear in Bit Load from the T Bit in SREG to a Bit in Branch if Bit in SREG is Branch if Bit in SREG is Branch if Carry Branch if Carry Branch if Branch if Greater or Equal (Signed).

2 Branch if Half Carry Flag is AVR Instruction Set Manual 2021 Microchip Technology Inc. ManualDS40002198B-page Branch if Half Carry Flag is Branch if Global Interrupt is Branch if Global Interrupt is Branch if Lower (Unsigned).. Branch if Less Than (Signed).. Branch if Branch if Not Branch if Branch if Same or Higher (Unsigned).. Branch if the T Bit is Branch if the T Bit is Branch if Overflow Branch if Overflow Bit Set in Bit Store from Bit in Register to T Bit in Long Call to a Clear Bit in I/O Clear Bits in Clear Carry Clear Half Carry Clear Global Interrupt Enable Clear Negative Clear Clear Sign Clear T Clear Overflow Clear Zero One s Compare with Compare with Compare Skip if Data Encryption Extended Indirect Call to Extended Indirect Extended Load Program Exclusive Fractional Multiply Fractional Multiply Fractional Multiply Signed with Indirect Call to Indirect - Load an I/O Location to Load and Load and AVR Instruction Set Manual 2021 Microchip Technology Inc.

3 ManualDS40002198B-page Load and Load Indirect from Data Space to Register using (LDD) Load Indirect from Data Space to Register using (LDD) Load Indirect From Data Space to Register using Load Load Direct from Data (AVRrc) Load Direct from Data Load Program Logical Shift Logical Shift Copy Copy Register Multiply Multiply Multiply Signed with Two s No Logical Logical OR with Store Register to I/O Pop Register from Push Register on Relative Call to Return from Return from Relative Rotate Left trough Rotate Right through Subtract with Subtract Immediate with Carry SBI Set Bit in I/O Set Bit in I/O Skip if Bit in I/O Register is Skip if Bit in I/O Register is Subtract Immediate from Set Bits in Skip if Bit in Register is Skip if Bit in Register is Set Carry Set Half Carry Set Global Interrupt Enable Set Negative Set all Bits in Set Sign Set T Set Overflow Set Zero (AVRe)

4 Store Program AVR Instruction Set Manual 2021 Microchip Technology Inc. ManualDS40002198B-page (AVRxm, AVRxt) Store Program Store Indirect From Register to Data Space using Index (STD) Store Indirect From Register to Data Space using Index (STD) Store Indirect From Register to Data Space using Index Store Direct to Data (AVRrc) Store Direct to Data Subtract Without Subtract Swap Test for Zero or Watchdog A Device Core DS40002198B - 02 DS40002198A - 05 - 11 - 04 - 07 07 04 07 05 Microchip Change Notification 163 Microchip Devices Code Protection 164 Quality Management 165 Worldwide Sales and AVR Instruction Set Manual 2021 Microchip Technology Inc. ManualDS40002198B-page 51. Instruction Set NomenclatureStatus Register (SREG)SREGS tatus RegisterCCarry FlagZZero FlagNNegative FlagVTwo s Complement Overflow FlagSSign FlagHHalf Carry FlagTTransfer BitIGlobal Interrupt Enable BitRegisters and OperandsRd:Destination (and source) register in the Register FileRr:Source register in the Register FileR:Result after Instruction is executedK:Constant datak:Constant addressb:Bit position ( ) in the Register File or I/O Registers:Bit position ( )in the Status RegisterX,Y,Z:Indirect Address Register (X=R27:R26, Y=R29:R28, and Z=R31:R30 or X=RAMPX:R27:R26,Y=RAMPY:R29:R28, and Z=RAMPZ:R31:R30 if the memory is larger than 64 KB)A:I/O memory addressq.

5 Displacement for direct addressingUUUnsigned Unsigned operandsSSSigned Signed operandsSUSigned Unsigned operandsMemory Space IdentifiersDS( )Represents a pointer to address in data spacePS( )Represents a pointer to address in program spaceI/O(A)I/O space address AI/O(A,b)Bit position b of the byte in I/O space address ARd(n)Bit n in register RdOperator Arithmetic multiplication AVR Instruction Set ManualInstruction Set Nomenclature 2021 Microchip Technology Inc. ManualDS40002198B-page 6+Arithmetic addition-Arithmetic subtraction Logical AND Logical OR Logical XOR>>Shift right<<Shift left==Comparison Assignment SwapxLogical complement of x (NOT x)StackSTACKS tack for return address and pushed registersSPThe Stack PointerFlags Flag affected by instruction0 Flag cleared by instruction1 Flag set by Instruction -Flag not affected by Instruction AVR Instruction Set ManualInstruction Set Nomenclature 2021 Microchip Technology Inc.

6 ManualDS40002198B-page 72. CPU Registers Located in the I/O RAMPX, RAMPY, and RAMPZR egisters concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space onMCUs with more than 64 KB data space, and constant data fetch on MCUs with more than 64 KB program RAMPDR egister concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with morethan 64 KB data EINDR egister concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs withmore than 64K words (128 KB) program space. AVR Instruction Set ManualCPU Registers Located in the I/O Space 2021 Microchip Technology Inc. ManualDS40002198B-page 83. The Program and Data Addressing ModesThe AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to theprogram memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory).

7 Thissection describes the various addressing modes supported by the AVR architecture. In the following figures, OPmeans the operation code part of the Instruction word. To simplify, not all figures show the exact location of theaddressing bits. To generalize, the abstract terms RAMEND and FLASHEND have been used to represent thehighest location in data and program space, : Not all addressing modes are present in all devices. Refer to the device specific Instruction Register Direct, Single Register RdFigure 3-1. Direct Single Register AddressingRdOPThe operand is contained in the destination register (Rd). Register Direct - Two Registers, Rd and RrFigure 3-2. Direct Register Addressing, Two RegistersOPRrRd AVR Instruction Set ManualThe Program and Data Addressing Modes 2021 Microchip Technology Inc. ManualDS40002198B-page 9 Operands are contained in the sources register (Rr) and destination register (Rd).

8 The result is stored in thedestination register (Rd). I/O DirectFigure 3-3. I/O Direct AddressingOPRr/RdAOperand address A is contained in the Instruction word. Rr/Rd specify the destination or source : Some AVR microcontrollers have more peripheral units than can be supported within the 64 locationsreserved in the opcode for I/O direct addressing. The extended I/O memory from address 64 and higher can only bereached by data addressing, not I/O Data DirectFigure 3-4. Direct Data AddressingData AddressOPRr/RdA 16-bit Data Address is contained in the 16 LSBs of a two-word Instruction . Rd/Rr specify the destination or sourceregister. The LDS Instruction uses the RAMPD register to access memory above 64 KB. AVR Instruction Set ManualThe Program and Data Addressing Modes 2021 Microchip Technology Inc. ManualDS40002198B-page Data IndirectFigure 3-5. Data Indirect AddressingX, Y OR Z - POINTERThe operand address is the contents of the X-, Y-, or the Z-pointer.

9 In AVR devices without SRAM, Data IndirectAddressing is called Register Indirect Data Indirect with Pre-decrementFigure 3-6. Data Indirect Addressing with Pre-decrementX, Y OR Z - POINTERThe X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contentsof the X-, Y-, or the Z-pointer. AVR Instruction Set ManualThe Program and Data Addressing Modes 2021 Microchip Technology Inc. ManualDS40002198B-page Data Indirect with Post-incrementFigure 3-7. Data Indirect Addressing with Post-incrementX, Y OR Z - POINTERThe X-, Y-, or the Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, orthe Z-pointer before Data Indirect with DisplacementFigure 3-8. Data Indirect with DisplacementY OR Z - POINTERqOPRr/RdThe operand address is the result of the q displacement contained in the Instruction word added to the Y- orZ-pointer.

10 Rd/Rr specify the destination or source register. AVR Instruction Set ManualThe Program and Data Addressing Modes 2021 Microchip Technology Inc. ManualDS40002198B-page Program Memory Constant Addressing using the LPM, ELPM, and SPMI nstructionsFigure 3-9. Program Memory Constant AddressingLSbZ - POINTERC onstant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. For LPM, the LSbselects low byte if cleared (LSb == 0) or high byte if set (LSb == 1). For SPM, the LSb should be cleared. If ELPM isused, the RAMPZ Register is used to extend the Program Memory with Post-increment using the LPM Z+ and ELPM Z+ InstructionFigure 3-10. Program Memory Addressing with Post-incrementLSbZ - POINTER1 Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. The LSb selects lowbyte if cleared (LSb == 0) or high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extendthe Z-register.