AVR Microcontroller with Core Independent …

1 ATmega324PB AVR Microcontroller with core Independent Peripheralsand PicoPower technologyIntroductionThe picoPower ATmega324PB is a low-power CMOS 8-bit Microcontroller based on the AVR enhancedRISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achievesthroughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for powerconsumption versus processing Performance, Low Power AVR 8-Bit Microcontroller Family Advanced RISC Architecture 131 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Throughput at 20 MHz On-Chip 2-cycle Multiplier High Endurance Non-Volatile Memory Segments 32 KBytes of In-System Self-Programmable Flash Program Memory 1 KBytes EEPROM 2 KBytes Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data Retention.

2 20 Years at 85 C Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security JTAG (IEEE std. Compliant) Interface Boundary-Scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits Through the JTAG Interface peripheral Features peripheral Touch Controller (PTC) Capacitive Touch Buttons, Sliders and Wheels 32 Self-Sap Channels and 256 Mutual Cap Channels Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode 2017 Microchip Technology Inc.

3 Datasheet CompleteDS40001908A-page 1 Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Ten PWM Channels 8-Channel 10-Bit ADC Differential Mode with Selectable Gain at 1 , 10 or 200 Three Programmable Serial USARTs Two Master/Slave SPI Serial Interfaces Two Byte-oriented 2-wire Serial Interfaces (Philips I2C Compatible) Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal 8 MHz Calibrated Oscillator External and Internal Interrupt Sources Six Sleep Modes.

4 Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and ExtendedStandby Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure Individual Serial Number to Represent a Unique ID I/O and Packages 39 Programmable I/O Lines 44-Pin TQFP and 44-Pin QFN /MLF Operating Voltage: - Temperature Range: -40 C to 105 C Speed Grade: 0 - 4 MHz @ - 0 - 10 MHz @ - 0 - 20 MHz @ - Power Consumption at 1 MHz, , 25 C Active Mode: Power-Down Mode: A Power-Save Mode: A (Including 32kHz RTC) ATmega324PB 2017 Microchip Technology Inc.

5 Datasheet CompleteDS40001908A-page 2 Table of Information .. Code CPU Arithmetic Logic Purpose Register 16-bit Execution and Interrupt Reprogrammable Flash Program Data Data Clock and Clock Systems and Their Frequency Crystal Power Crystal Internal RC Internal 2017 Microchip Technology Inc. Datasheet CompleteDS40001908A-page Output Clock - Clock Failure Detection - Power Management and Sleep Noise Reduction Standby Reduction Power - System Control and the System Voltage Vectors in - External as General Digital Port ATmega324PB 2017 Microchip Technology Inc.

6 Datasheet CompleteDS40001908A-page - 8-bit Timer/Counter0 with Clock Compare Match Output of Timing , 3, 4 - 16-bit Timer/Counter1, 3, 4 with 16-bit Timer/Counter Clock Capture Match Output Compare of Timing 0, 1, 3, 4 Clock Clock - 8-bit Timer/Counter2 with PWM and Asynchronous Clock Compare Match Output of Timing Operation of - Output Compare Serial peripheral 207 ATmega324PB 2017 Microchip Technology Inc. Datasheet CompleteDS40001908A-page Pin - Universal Synchronous Asynchronous Receiver Transmission The USART Reception The USART Data Communication of Baud Rate - USART in SPI Data Modes and USART MSPIM vs.

7 AVR - 2-wire Serial Serial Interface Bus Transfer and Frame Bus Systems, Arbitration, and of the TWI the Systems and - Analog Comparator Multiplexed - Analog to Digital 289 ATmega324PB 2017 Microchip Technology Inc. Datasheet CompleteDS40001908A-page a and Conversion Channel or Reference Noise Conversion - peripheral Touch Interface and On-chip Debug Test Access the Boundary-scan the On-chip Debug Debug Specific JTAG the JTAG Programming (JTAG) Specific JTAG Boundary-scan Description Language - Boot Loader Support Read-While-Write and Boot Loader Flash and No Read-While-Write Flash the Boot Loader Loader Lock the Flash During the Memory And Data Memory Lock ATmega324PB 2017 Microchip Technology Inc.

8 Datasheet CompleteDS40001908A-page Programming Parameters, Pin Mapping, and Via the JTAG Maximum and Reset Timing Serial Interface Programming Supply Supply Current of IO Modules .. Supply Driver Threshold and Comparator Oscillator Consumption of peripheral Consumption in Reset and Reset Pulse Set J - Revision 438 The Microchip Web 440 Customer Change Notification ATmega324PB 2017 Microchip Technology Inc. Datasheet CompleteDS40001908A-page 8 Customer 440 Microchip Devices Code Protection 441 Quality Management System Certified by Sales and ATmega324PB 2017 Microchip Technology Inc.

9 Datasheet CompleteDS40001908A-page 91. DescriptionThe ATmega324PB is a low-power CMOS 8-bit Microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achievesthroughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for powerconsumption versus processing AVR core combines a rich instruction set with 32 general purpose working registers. All the 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two Independent registers tobe accessed in a single instruction executed in one clock cycle.

10 The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC ATmega324PB provides the following features: 32K bytes of In-System Programmable Flash withRead-While-Write capabilities, 1 Kbytes EEPROM, 2 Kbytes SRAM, 39 general purpose I/O lines, 32general purpose working registers, five flexible Timer/Counters with compare modes, internal andexternal interrupts, three serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), twoSPI serial port, a 8-channel 10-bit ADC with optional differential input stage with programmable gain, aprogrammable Watchdog Timer with internal Oscillator, IEEE std.