CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input ...

1 IN_MUX LVPECLR eference GeneratorVEEVCCVCCVCCVCCVCC1010QP( )QN( )CLKP0 CLKN0 CLKP1 CLKN1 CLK_SELVBB++ CDCLVP111 ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityCDCLVP111 SCAS859F JANUARY2009 REVISEDJUNE2015 CDCLVP111 Low-Voltage1:10 LVPECLWith SelectableInput Clock Driver1 Features3 DescriptionTheCDCLVP111clockdriverdistri butesone1 DistributesOne DifferentialClockInputPairdifferentialcl ockpair of LVPECL Input ,(CLK0,CLK1)LVPECLto 10 DifferentialLVPECLto ten pairsof differentialLVPECL clock(Q0,Q9) FullyCompatibleWithLVECLand LVPECL outputswith minimumskewfor Supportsa WideSupplyVoltageRangefromCDCLVP111can accepttwo clocksourcesinto to Vdesignedfor driving50- SelectableClockInputThroughCLK_SELan outputpin is notused,leavingit openis Low-OutputSkew(Typical15 ps)

2 For Clock-recommendedto onlyDistributionApplicationsone of the outputpins froma differentialpair is used,the otheroutputpin mustbe identicallyterminatedto AdditiveJitterLessThan1 ps50 . PropagationDelayLessThan350 psTheVBBreferencevoltageoutputis usedif single- OpenInputDefaultStateendedinputoperation is this case,the LVDS,CML,SSTLI nputCompatibleVBBpin shouldbe connectedto CLK0and bypassed VBBR eferenceVoltageOutputfor Single-Endedto GNDthrougha ,for high-speedperformanceup to GHz, Availablein a 32-PinLQFPand QFNP ackagethe differentialmodeis stronglyrecommended.

3 FrequencyRangeFromDC to GHzTheCDCLVP111deviceis characterizedfor Pin-to-PinCompatibleWithMC100 SeriesEP111,operationfrom 40 C to 85 ,LVEP111,PTN1111 DeviceInformation(1)2 ApplicationsPARTNUMBERPACKAGEBODYSIZE(NO M) Designedfor Driving50- TransmissionLinesVQFN(32) (32) HighPerformanceClockDistribution(1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand JANUARY2009 Applicationsand Pin Configurationand ElectricalCharacteristics, Deviceand ElectricalCharacteristics, Mechanical,Packaging,and RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (July2011)to RevisionFPage AddedDeviceInformationTable,Pin Configurationand Functions.

4 Specifications;Applicationsand Implementation;DetailedDescription;Layou t;Deviceand DocumentationSupport;Mechanical,Packagin g,and 1 Addedextendedfrequencyrangefrom1 GHzdownto (March2010)to RevisionEPage Changedthe PowerPADPin (November2009)to RevisionDPage Deletedduplicateinformationcoveringthe PowerPADfromNote1 of the Pin Changedthe PowerPADdescriptionin the PIN FUNCTIONS tableto includethe Added"NOTE" at the beginningof "Applicationsand Implementation" ChangedJEDEC symbolto R (April2009)to RevisionCPage ChangedPowerPADinformationto the AddedPowerPADinformationto the Pin (March2009)to RevisionBPage Changedrecommendedresistorvaluesin.

5 162 SubmitDocumentationFeedbackCopyright 2009 2015, JANUARY2009 REVISEDJUNE2015 ChangesfromOriginal(January2009)to RevisionAPage Changednotereferneceswithinthe AC Addeda Typ valueof the Additivephasejitter in the AC 2009 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks: CDCLVP111 PowerPAD(0) CDCLVP111 SCAS859F JANUARY2009 Pin Configurationand FunctionsRHB,VF, or VFPP ackage32-PinVQFN,LQFP,or HLQFPTop ViewPin Functions(1) selectbetweenCLK0and ,CLK04 InputDifferentialLVECL/ LVPECL inputpair6 CLK1,CLK171113151820Q [9:0]OutputLVECL/ LVPECL clockoutputs,theseoutputsprovidelow-skew copiesof [9:0]OutputLVECL/ LVPECL complementaryclockoutputs,theseoutputspr ovidecopiesof Referencevoltageoutputfor single-endedinputoperation(1)CLKn,CLK_SE Lpulldownresistor= 75 k ; CLKnpullupresistor= ; CLKnpulldownresistor= 50 k.

6 4 SubmitDocumentationFeedbackCopyright 2009 2015, JANUARY2009 REVISEDJUNE2015 Pin Functions(1)(continued) negativesupplyvoltagein ECLmodeThe PowerPADof the QFN32is thermallyconnectedto the die to improvethe heattransferPowerPAD 0 Groundout of the pad of the QFN32with PowerPADmustbe connectedto (unlessotherwisenoted)(1)MINMAXUNITVCCS upplyvoltage(Relativeto VEE) + + 20mAVEEN egativesupplyvoltage(Relativeto VCC) 11mAIODC outputcurrent 50mATJM aximumoperatingjunctiontemperature125 CTstgStoragetemperature 65150 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

7 Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay (HBM),per ANSI/ESDA/JEDECJS-001(1)3000V(ESD)Electr ostaticdischargeVCharged-devicemodel(CDM ),per JEDEC specificationJESD22-1500C101(2)(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.(2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (relativeto VEE) 4085 C/WTJO peratingjunctiontemperature110 CCopyright 2009 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks: CDCLVP111 ILIHVV- CDCLVP111 SCAS859F JANUARY2009 (1)RHB(VQFN)VF (LQFP)UNIT32 PINSR C/WR JC(top)Junction-to-case(top) C/WR C/W C/W C/WR JC(bot)Junction-to-case(bottom) C/W(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport, ElectricalCharacteristics,LVECLV supply.

8 VCC= 0 V, VEE= to V overoperatingfree-airtemperaturerange(un lessotherwisenoted)PARAMETERTESTCONDITIO NSMINTYPMAXUNITS upplyinternalIEEA bsolutevalueof current 40 C, 25 C, 85 C4085mAcurrent 40 C354 Outputand internalICCAll outputsterminated50 to VCC 2 V25 C380mAsupplycurrent85 C405 Includespullup/pulldownresistors,IINI nputcurrent 40 C, 25 C, 85 C 150150 AVIH= VCC, VIL= VCC- 2 VFor VEE= 3 to V, 40 C, 25 C, 85 C mAInternallygeneratedVBBV bias voltageVEE= , 40 C, 25 C, 85 C mAHigh-levelinputVIH 40 C, 25 C, 85 C (CLK_SEL)Low-levelinputVIL 40 C, 25 C, 85 C (CLK_SEL)InputamplitudeVID 40 C, 25 C, 85 (CLKn,CLKn)Differenceof Input ,see(1)Common-modeVCMDC offsetrelativeto VEE 40 C, 25 C, 85 CVEE+ 1 (CLKn,CLKn) 40 C 21 mA25 C C 40 C 5 mA25 C C 50 toVOD 40 C, 25 C, 85 C600mVvoltageswingVCC 2 V, see Figure5(1)VIDminimumand maximumis requiredto maintainac specifications,actualdevicefunctiontoler atesa minimumVIDof 100 2009 2015, JANUARY2009 ElectricalCharacteristics,LVPECLV supply.

9 VCC= to V, VEE= 0 V overoperatingfree-airtemperaturerange(un lessotherwisenoted)PARAMETERTESTCONDITIO NSMINTYPMAXUNITIEES upplyinternalcurrentAbsolutevalueof current 40 C, 25 C, 85 C4085mA-40 C354 Outputand internalICCAll outputsterminated50 to VCC 2 V25 C380mAsupplycurrent85 C405 Includespullup/pulldownresistorsIINI nputcurrent 40 C, 25 C, 85 C 150150 AVIH=VCC, VIL= VCC 2 VVCC= 3 to V, IBB= mA 40 C, 25 C, 85 CVCC ,bias voltage 40 C, 25 C, 85 CVCC mAHigh-levelinputvoltageVIH 40 C, 25 C, 85 CVCC (CLK_SEL)Low-levelinputvoltageVIL 40 C, 25 C, 85 CVCC (CLK_SEL)Inputamplitude(CLKn,VID 40 C, 25 C, 85 )Differenceof inpu,see(1),Common-modeVCMDC offsetrelativeto VEE 40 C, 25 C, 85 C1 VCC (CLKn,CLKn) 40 CVCC 21 mA25 CVCC CVCC 40 CVCC 5 mA25 CVCC CVCC 50 toVOD 40 C, 25 C, 85 C600mVvoltageswingVCC- 2 V, see Figure5(1)VIDminimumand maximumis requiredto maintainac specifications,actualdevicefunctiontoler atesa minimumVIDof 100 ElectricalCharacteristicsVsupply.

10 VCC= to V, VEE= 0 V or LVECL/ LVPECL inputVCC= 0 V, VEE= to V overoperatingfree-air temperaturerange(unlessotherwisenoted)PA RAMETERTESTCONDITIONSMINTYPMAXUNITD ifferentialpropagationdelayCLKn,tpdSee NoteD in Figure2200350psCLKnto all Q0, Q9, Q9tsk(o)Output-to-outputskewSee NoteA in Figure21530pstsk(pp)Part-to-partskewSee NoteB in Figure270psIntegrationbandwidthof 20 kHz to 20 MHz, < = 125 MHzat 25 Cf(max)MaximumfrequencyFunctionalup to GHz3500 MHztr/tfOutputrise and fall time (20%,80%)See NoteD in Figure290200psCopyright 2009 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks: CDCLVP111 Output Frequency [GHz]VOD [V] - Differential Output Voltage VCC= , TA=25 CCDCLVP111 SCAS859F JANUARY2009 LVPECLI nputUsingCLK0 Pair,VCM= 1 V, VID= V8 SubmitDocumentationFeedbackCopyright 2009 2015, JANUARY2009 REVISEDJUNE20157 calculatedas the greaterof: The differencebetweenthe fastestand the slowesttPLHn(n = 0, 1.)