Transcription of ChinalntegratedCircult CIC 中国集成电路
1 China lntegrated CircultCIC2014 12 http 187 CorePowerDeliveryNetworkAnalysisofCorean dCorelessSubstratesinaMultilayerOrganicB uildupPackageOzgurMisman,MikeDeVita,Noza dKarim AmkorTechnology,Inc.,1900 SouthPriceRoad,Chandler,AZ85286,USA Abstract:The use of flip chip organic buildup substrates is a popular choice for large Application Specific IntegratedCircuits ASICs due to the high routing density they offer at a relatively reasonable cost. A typical buildup packageconsists of multiple high density routing layers buildup layers supported by a thick core. The laminate core addsrigidity to the substrate and can be configured to various thicknesses such as 400 m, 600 m and 800 m. Corelesssubstrates are an emerging technology targeted to increase the routing density, lower the package z height, whileproviding better electrical performance. This is primarily due to the replacement of thick core layers with a thinbuildup layer. As the trend for higher levels of performance and system bandwidth continues, coreless technology iswell positioned as an enabling technology this paper we compare the performance of the core power delivery network Core-PDN of two 31mm, 900 ball, 8layer organic flip chip buildup substrates.
2 We first analyze the substrates in the frequency domain and then evaluatethe transient response under various switching conditions. Both packages are designed identically except for the core Ozgur Misman Mike DeVita NozadKarim ASICs build-up 400 m,600 m, 800 m 8 31mm 900 PDN 50 MHz 2 GHz S PDN PDN ; ; 53 CIC China lntegrated Circult http 187 2014 12 1(b) 12 1(a) 12 2 versus coreless substrate construction. Two-port high frequency S parameter measurements between 50 MHz and2 GHz are carried out using a Vector network Analyzer VNA to characterize the PDN in the frequency domain. Bothsimulated and measured data are correlated in the frequency domain.
3 Time domain response of PDN to current tran-sients with various switching conditions are simulated and : power delivery network ; Coreless Substrate; Flip Chip Package; Build-up Substrate; Electrical Perfor-mance1 Core-PDN PDN PDN PDN PDN / 800 m 400 m 600 m PDN <400 m [1] 1 a 1 b 3-2-3 5-2-5 3-4-3 2 5-2-5 54 China lntegrated CircultCIC2014 12 http 187 3 - 4 / 1 / 2 HVM 25 m / microstrip stripline o o o o 1 o o 2 o PDN o IR IR-Drop o o 2 31mm 900 8 fcBGA PDN VNA / bump
4 3 8720D 250 m - - 50 VNA OSLT 50 MHz 2 GHz / / PDN / 4 55 CIC China lntegrated Circult http 187 2014 12 7 6(a) - 6(b) - 5 / BGA- S / Istvan Novak [2] BGA 5 / BGA / 3 / A B C 3D Cadence PowerSI 3D / VNA 6 a 6 b 7 1 GHz 8 75pH 96pH 20% 56 China lntegrated CircultCIC2014 12 http 187 9 10 150ps 300ps 300ps 11(a)
5 PDN 8 20%4 PDN Core-PDN PDN core-switching VDD VDD 5-10% 9 A edge rate 150ps 300ps V BGA 3D CadenceSpeed2000 374 BGA 59 655 MHz 150ps 300ps 10 PDN 150ps 300ps PDN PDN PDN 11 a 11 b 3 +/-56% +/-9% 57 CIC China lntegrated Circult http 187 2014 12 3 11(b) PDN 1 GHz PDN 5 Core-PDN IPC IPC 2013 9 Chandler [3] [1] GaWon Kim, SeungJae Lee, JiHeon Yu, GyuIckJung, JinYoung Kim, Nozad Karim, HeeYeoul Yoo andChoonHeung Lee , Advanced Coreless Flip-chip BGAP ackage with High Dielectric Constant Thin Film Em-bedded Decoupling Capacitor , in proceedings of 2011 Electronic Components and Technology Conference, [2] Istvan Novak, PicoHenrys in power DistributionNetworks , DesignCon 2000[3] Ozgur Misman, Mike DeVita, Nozad Karim, "IPCC onference on Component Technology: Closing the Gapin the Chip to PCB Process," Chandler, AZ , September10-12 2013 Ozgur Misman Amkor SiP Mike DeVita Amkor SiP Nozad Karim Amkor SiP 58
