Choose the right data converter for your application

1 Choose the right A/D converter for your applicationAgenda Analog-to-Digital-Converters (ADCs) What are the Signal Frequencies Analog Classes of applications Frequency ranges of ADCs Nuts and Bolts of Delta-Sigma Converters The SAR ADC The High-speed Pipeline Topology Digital-to-Analog-Converters (DACs) R-2R-DACs String-DACs Multiplying DACs Delta-Sigma DACs High-Speed Current-Steering DACsReal World vs. BandwidthBandwidth (Hz)Noise Free Resolution (bits)1101001k051015202510k100k1 MTempPressureLoadFlowLevelDisplacement/P roximityPhoto Sensing10M100 MCommunicationsDefenseImagingTest & Measurement1 GADC Architectures There are many different ADC Architectures Successive Approximation (SAR) Delta-Sigma ( ) Pipeline (Flash)

2 Delta-Sigma converters determine the digital word by Oversampling Applying Digital Filtering SARs determine the digital word by Sampling the input signal Using an iterative process Pipeline converters determine digital word by Undersampling With Sample / Gain Algorithm Topology Multiple stages / Larger Cycle-latency Delta SigmaOr Sigma Delta(Oversampling)SAR Successive ApproximationConversion Rate1K1001010K100K1M10M100M242016128 converter Resolution (bits)ADC Technologies - AdvantagesAdvantages High Resolution High Stability(averages and filters out noise) Low Power Low costDisadvantagesDisadvantages Cycle-Latency Low SpeedPipelineSPSADS1610 ADS1610 10 M 1610 M 16--bitbitADS1672 ADS1672 625k 24625k 24--bitbitADS1675 ADS1675 4 M 244 M 24--bitbit Delta SigmaOr Sigma Delta(Oversampling)SAR Successive ApproximationConversion Rate1K1001010K100K1M10M100M242016128 converter Resolution (bits)

3 ADC Technologies - SARA dvantagesAdvantages Zero-cycle Latency Low Latency-time High Accuracy Typically Low Power Easy to UseDisadvantagesDisadvantages Max Sample Rates 2-5 MHzPipelineSPS Delta SigmaOr Sigma Delta(Oversampling)SAR Successive ApproximationConversion Rate1K1001010K100K1M10M100M242016128 converter Resolution (bits)ADC Technologies - pipelineAdvantagesAdvantages Higher Speeds Higher BandwidthDisadvantagesDisadvantages Lower Resolution Pipeline Delay/Data Latency More powerPipelineSPSS electing ADC TopologyModerate cost. 31-bit 24-bit 16-bit 4ksps 4 Msps 10 MspsDelta-Sigma 16-bit 14-bit 12-bit 200 Msps 250 Msps 550 MspsPipelineSimple operation, low cost, low power.

4 16-bit 18-bit 4 Msps ConversionADC TopologyFast, expensive, higher power ADC Architecture to Use??ConstantScales withSample RateScales withSample Rate or ConstantPower Consumption-+++Capability to convert non-periodic multiplexed signals0+++Suitability for convertingMultiple Signals per ADC0+++Latency (Sample-to-Output)+++0 Resolution (ENOB)0/++++Throughput (samples/sec)Delta SigmaSARP ipelinedCharacteristicApplications for Converters Signal Level System clock range ~ to 40 MHz Has an Internal Digital Low-Pass Filter Uses an integrator Accurate near DC High Resolution up to 24 bits Audio System clock range ~ 20 to 40 MHz Has an Internal Digital Low-Pass Filter Optimized noise performance Optimized filter in audio frequency for flatness Delta-Sigma A/D ConvertersDelta-SigmaModulatorAnalogInpu tDigitalFilterDecimatorDigitalOutputDigi tal Decimating Filter(usually implemented as a single unit)SAMPLE RATE (Fs)

5 DATA RATE (Fd)Fs / Fd = DR(DR = Decimation Ratio)Input to the Delta-Sigma A/DDelta-SigmaModulatorAnalogInputDigita lFilterDecimatorDigitalOutputDigital Decimating Filter(usually implemented as a single unit)You are hereSAMPLE RATE (Fs)DATA RATE (Fd)Fs / Fd = DR(DR = Decimation Ratio)Input SignalMAGNITUDEFREQUENCYTIMEAMPLITUDEI nput Signal:TIME DOMAINI nput Signal:FREQUENCY DOMAINM odulator OutputDelta-SigmaModulatorAnalogInputDig italFilterDecimatorDigitalOutputDigital Decimating Filter(usually implemented as a single unit)SAMPLE RATE (Fs)DATA RATE (Fd)Fs / Fd = DR(DR = Decimation Ratio)1stOrder Delta-Sigma ModulatorTIME DOMAINTIMEAMPLITUDEIN(Analog)OUT(Digital )Sigma (Integrator)Delta+-++1-bitDACyieixi1-SAM PLE DELAY1-bit ADC01 Believe it or not, the sinewave is in there!

6 (drawing is approximate)Modulator Output SignalModulator Output:TIME DOMAINM odulator Output:FREQUENCY DOMAIN01 Believe it or not, the sinewave is in there!(drawing is approximate)QUANTIZATIONNOISEFsSIGNALA nalog SignalFrequencyFSFirst Order ModulatorSecond Order ModulatorThird Order ModulatorMulti-order Delta-Sigma ModulatorsDelta-Sigma A/D Signal PathDelta-SigmaModulatorAnalogInputDigit alFilterDecimatorDigitalOutputDigital Decimating Filter(usually implemented as a single unit)SAMPLE RATE (Fs)DATA RATE (Fd)Fs / Fd = DR(DR = Decimation Ratio)Input Outputdelaydelaydelayb1b2b3bi24 Digital Filter FunctionHigh Frequency Noise ReductionSinc3 Filter responseTIME DOMAIN8000007 FFFFF0000000 Outcome of Digital Filter FunctionDecimation Digital FilterDelta-SigmaModulatorAnalogInputDig italFilterDecimatorDigitalOutputDigital Decimating Filter(usually implemented as a single unit)SAMPLE RATE (Fs)DATA RATE (Fd)Fs / Fd = DR(DR = Decimation Ratio)Input Outputdelay8000007 FFFFF0000000delaydelay1/Fs24241/Fd(DR)De cimator Function: AveragerSIGNAL PRODUCED BY DIGITAL FILTERFUNCTION8000007 FFFFF0000000 Decimator Function.

7 Pick & Dump8000007 FFFFF0000000@ Sampling Rate@ Data RateOUTPUT OFECOMOMICALDECIMATORQUANTIZATIONNOISEFs SIGNALFdFs / Fd = DR = KQUANTIZATIONNOISEFsSIGNALFdA. B. DRA> DRBS ampling speed vs. SNRA dditional Features s often have additional features for data acquisition Analog PGA (ADS1282, ADS1248/7/6, ADS1230/2) Input Buffer (ADS1222/4/5/6, ADS1245, ADS1259) Burnout Current Sources (ADS1243/44) Multiplexers (most ADS12xx) More complete system solution (ADS1248, ADS1115) Sensor Excitation (ADS1248/7) Most Serial ADCs are SARs or Delta-Sigmas SARs are Best for General Purpose Apps Data Loggers, Temp Sensors, Bridge Sensors, General Purpose In the Market SARs Can be 8 to 18 bits of resolution Speed range.

8 > DC to < 5 Msps SARs found as Stand-alone Peripheral in Microcontrollers, ProcessorsThe SAR ADC SARA nalog to Digital converter ?How Does a SAR work? Similar to a balance scale 1??1 ?1?1 the MSB is determined firstthe LSB is determined lastMSB1mid0 LSB1 SAR Conversion ConceptAnalog inputVINFS01/4FS1/2FS3/4 FSTEST MSBTEST MSB -1 TEST LSBTEST MSB -2 Bit = 1 Bit = 0 Bit = 1 Bit = 0 Digital Output Code = 1010 ADC OutputTimeRS1 CSHVSH0+S1S2 SAR ADCVCSHVINRINCINVOPSAR converter Input StageNote: All capacitors must be able to charge to LSB within the acquisition time!

9 Additional Features Fewer options with SARs Some converters have multiplexers (ADS82xx) References (ADS78xx, ADS84xx, ADS85xx, etc.) Input Buffers/Drivers (ADS8254/55/84) PGA (ADS7870/71) Programmable Alarm Level Comparator (ADS795x)High Speed Pipeline Topology Pipeline converters fit high-speed applications (5 MHz to >100 MHz). Applications where you typically find pipeline converters are: Wireless and Line Communications Test and Measurement, Instrumentation Medical Imaging Radar Systems Data AcquisitionPipeline A/D ConverterArchitecture Overview++--VINBit iBit 1, MSBBit n, LSBS tage 12-BitA/D2-BitD/ADelayn Latches Delayn-1 Latches2-BitA/D2-BitD/A S/H2S/H1 Digital Error CorrectionOutput LatchesGain = 2 SystemADCD igital Processing,DDCDSPA nalogFront-endDiff/SESignal ConditioningBandpass FilteringGain to Match FSR of A/DSE to Diff ConversionDC-level shiftingConversion digitizationmixing (alias)

10 Digital ProcessingFrequency TranslationDecimationProcessing Gain (SNR)DSPA nalog DigitalWhat s the application ?Time Domain Imaging (CCD) Camcorders Digital Cameras Scanner RGB/Comp. Video Test Instrumentation Medical Important Specs: SNR Slew-Rate/ tset DNL DC-Accuracy/ DriftFrequency Domain Communications Set-Top Box Cable Modem Basestation IF Digitizer GPS Frequency Synthesizer Important Specs: SFDR ENOB Analog Input Bandwith Jitter31 ADC Interface SolutionsPrinciple Configuration ChoicesSingle-Ended Input (SE) Differential Input (DE)ADCADCI nput+ fsVcm-fsVcmININININ+ fs/2 Vcm-fs/2 + fs/2 Vcm-fs/2 Requires full input swing from +fs to fs2x the swing compared to differentialInput signal at IN typically requires a common-mode voltage for biasInput IN\ also requires a Vcm for correct dc-biasCombined Differential inputs result in full-scale input of +fs to fsEach input only requires the swing compared to single-endedBoth inputs require a Vcm for correct dc-bias21SE vs.