CMOS Phase-Locked-Loop Applications (Rev. B) - TI.com

1 Application Report SCHA003B - September 2002. CMOS Phase-Locked-Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A. W. M. Austin Standard Linear & Logic ABSTRACT. Applications of the HC/HCT4046A phase- locked loop (PLL) and HC/HCT7046A PLL with lock detection are provided, including design examples with calculated and measured results. Features of these devices relative to phase comparators, lock indicators, voltage-controlled oscillators (VCOs), and filter design are presented. Contents Introduction .. 4. Basic Loop Operation .. 4. Description of the HC/HCT4046A .. 6. Phase Comparators (PCs) .. 8. Operation of Phase Comparator PC1 .. 9. Operation of Phase Comparator PC2.

2 9. Operation of Phase Comparator PC3 (HC/HCT4046A Only) .. 12. Lock Indicators .. 13. PCPout of the HC/HCT4046A .. 13. Lock Detector of the HC/HCT7046A .. 13. Voltage-Controlled Oscillator (VCO) .. 15. VCO Description .. 15. VCO Frequency Control .. 17. VCO Parametric Ranges and Restrictions .. 22. Design Examples With Measured and Calculated Results .. 23. Design Examples With and Without Offset .. 27. Example With Offset .. 28. Example Without Offset .. 29. Rules of Thumb for Quick Calculations .. 30. Tabulated Solutions .. 31. Filter Design for the HC/HCT4046A .. 31. Loop Examples .. 32. LPF Using PC1 (Example 1) .. 32. Using PC2 With a Lag-Lead Filter (Example 2).

3 36. Simple LPF Using PC2 (Example 3) .. 37. Simple LPF Using PC2 With Divide-by-N (Example 4) .. 37. Simple RC LPF Using Frequency Offset and PC2 (Example 5) .. 38. 1. SCHA003B. LPF Design Summary .. 39. Bibliography and References .. 40. Acknowledgments .. 40. Appendix A Phase-Comparator Summary Information .. 41. Appendix B Loop Parameters and Equations .. 43. Appendix C Basic Program for VCO Frequency Calculations .. 46. Appendix D R1, R2, and C1 Values With Calculated fosc PC Solutions From Equations 3, 4, and 5 (VCC = 6 V) .. 49. Appendix E HC4046A PLL Layout With Simple RC Filter (R3C2) .. 50. List of Figures 1 Block Diagram of an HC/HCT4046A in a Typical PLL Circuit.

4 4. 2 Block Diagram of an HC/HCT4046A With External Loop Filtering .. 6. 3 HC/HCT4046A Functional Block Diagram .. 7. 4 HC/HCT7046A Functional Block Diagram .. 8. 5 PC1 Average Output Voltage as a Function of Input Phase Difference .. 9. 6 Typical Waveforms for PLL With PC1 Loop locked at fo .. 10. 7 PC2 Average Output Voltage as a Function of Input Phase Difference .. 11. 8 Typical Waveforms for PLL With PC2 Loop locked at fo .. 11. 9 PC3 Average Output Voltage as a Function of Input Phase Differences .. 12. 10 Typical Waveforms for PLL With PC3 Loop locked at fo .. 12. 11 Lock-Detector Circuitry in the HC/HCT7046A .. 13. 12 Waveform at Lock-Detector Capacitor When in Lock.

5 14. 13 Graph For Determining Value of Lock-Detector Capacitor .. 14. 14 Waveforms at Lock-Detector Capacitor When Unlocked .. 15. 15 VCO Portion of CD74HC4046A/7046A Functional Block Diagram .. 16. 16 Equivalent HC/HCT4046A Charge Circuit of the VCO .. 17. 17 HC/HCT4046A VCO Waveforms .. 18. 18 Current Multiplier Ratio M2 as a Function of R2 Bias Current .. 18. 19 Mirror Current as a Function of R2 Bias Current, Showing Range of Linearity .. 19. 20 Mirror Current as a Function of R1 Bias Current, Showing Range of Linearity (Pin 9 VCOin = VCC) .. 19. 21 Mirror Current as a Function of R1 Bias Current, Showing Range of Linearity (Pin 9 VCOin = VCC) .. 20. 22 VCO Frequency as a Function of VCOin (Measured and calculated values are shown.)

6 R1 = R2 = 10 kW, C1 = 47 pF, Cs = 6 pF, Tpd = 11 ns at VCC = 5 V, and Tpd = 15 ns at VCC = 3 V) .. 23. 23 HC/HCT4046A PLL VCO Test Circuit .. 24. 24 VCO Frequency as a Function of VCOin, Showing Effects of Different Values of R1 and R2 (10 kW and 100 kW) .. 24. 2 CMOS Phase-Locked-Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A. SCHA003B. 25 VCO Frequency and Power-Supply Current as a Function of Operating Voltage VCC, Showing Effects of Different Values of R2 (5 kW and 10 kW).. 25. 26 VCO Frequency as a Function of VCOin, Showing Effects of Different Values of R1 and R2 (10 kW and 1 MW) .. 26. 27 VCO Frequency as a Function of VCOin, Showing Duty-Cycle Control Obtained by Splitting Capacitor C1 and Controlling the Ratio of C1A and C1B.

7 27. 28 Evaluation Circuit and Waveforms for Data in Figure 27 .. 27. 29 Forms of LPF and Associated Loop Equations .. 35. E 1 HC4046A PLL Layout With Simple RC Filter (R3C2) .. 49. List of Tables 1 Results for Simple LPF Using PC2 With Divide-by-N .. 38. 2 Results for Simple RC LPF Using Frequency Offset and PC2 .. 39. CMOS Phase-Locked-Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A 3. SCHA003B. Introduction This application report provides the circuit designer with information on the use of the HC/HCT4046A phase- locked loop (PLL) devices with a voltage-controlled oscillator (VCO) and the HC/HCT7046A PLL devices with in-lock detection in phase- locked circuits.

8 A description of the basic loop operation is included as an introduction to phase-lock techniques. Complete circuit designs, with and without a frequency-divide ratio, are included as examples. Examples also are given of various filters operating over a range of frequencies. Basic Loop Operation The HC/HCT4046A PLL with VCO is a high-speed CMOS IC designed for use in general-purpose PLL Applications , including frequency modulation, demodulation, discrimination, synthesis, and multiplication. Specific Applications include data synchronizing, conditioning and tone decoding, as well as direct VCO use for voltage-to-frequency conversion and speed-control Applications .

9 The IC contains a VCO and a choice of phase comparators (PCs) for support of the basic PLL. circuit, as shown in Figure 1. The low-pass filter (LPF) is an essential part of the loop and is needed to suppress noise and high-frequency components. An optional fourth part of the loop is the divide-by-N frequency divider, which is needed when the VCO is run at a multiple of the signal-input reference frequency. To facilitate support of a variety of general-purpose Applications , both the filter and divider are external to the HC/HCT4046A. These and other aspects of the application of the HC/HCT4046A are explained in the following paragraphs through a variety of loop-design examples.

10 Figure 1. Block Diagram of an HC/HCT4046A in a Typical PLL Circuit HC/HCT4046A refers to the CD54HC4046A, CD74HC4046A, CD54 HCT4046A, and CD74 HCT4046A devices. HC/HCT7046A refers to the CD54HC7046A, CD74HC7046A, CD54 HCT7046A, and CD74 HCT7046A devices. 4 CMOS Phase-Locked-Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A. SCHA003B. For a full treatment of PLL theory, the reader is directed to the Bibliography and References, section where there are a number of references that support the descriptions and explanations given in this application report. The symbols and terminology used in this application report primarily follow the book, Phase-Lock Techniques.