Cortex-M3 Technical Reference Manual - Keil

1 Copyright 2005-2008 ARM Limited. All rights DDI 0337 GCortex -M3 r2p0 Technical Reference Manual iiCopyright 2005-2008 ARM Limited. All rights DDI 0337 GUnrestricted AccessCortex-M3 Technical Reference ManualCopyright 2005-2008 ARM Limited. All rights InformationThe following changes have been made to this NoticeWords and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright product described in this document is subject to continuous developments and improvements.

2 All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the the term ARM is used it means ARM or any of its subsidiaries as appropriate .Confidentiality StatusThis document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document Access is an ARM internal HistoryDateIssueConfidentialityChange15 December 2005 AConfidentialFirst Release13 January 2006 BNon-ConfidentialConfidentiality status amended10 May 2006 CNon-ConfidentialFirst Release for r1p027 September 2006 DNon-ConfidentialFirst Release for r1p113 June 2007 ENon-ConfidentialMinor update with no Technical changes11 April 2008 FConfidentialLimited release for SC300 r0p026 June 2008 GNon-ConfidentialFirst Release for r2p0 ARM DDI 0337 GCopyright 2005-2008 ARM Limited.

3 All rights AccessConfidentialProduct StatusThe information in this document is Final (information on a developed product).Web ivCopyright 2005-2008 ARM Limited. All rights DDI 0337 GUnrestricted AccessARM DDI 0337 GCopyright 2005-2008 ARM Limited. All rights AccessNon-ConfidentialContentsCortex-M3 Technical Reference ManualPrefaceAbout this book .. xxFeedback .. xxvChapter the processor .. , hierarchy, and implementation .. pipeline stages .. Unit .. target forwarding .. buffers .. revisions .. 1-19 Chapter 2 Programmer s the programmer s model .. access and user access .. types .. formats .. set summary .. 2-13 ContentsviCopyright 2005-2008 ARM Limited.

4 All rights DDI 0337 GNon-ConfidentialUnrestricted AccessChapter 3 System of processor registers .. 3-2 Chapter 4 Memory the memory map .. memory table .. 4-7 Chapter the exception model .. types .. priority .. and stacks .. control transfer .. up multiple stacks .. model .. levels .. 5-34 Chapter 6 Clocking and .. reset modes .. 6-5 Chapter 7 Power power management .. power management .. 7-3 Chapter 8 Nested Vectored Interrupt the NVIC .. programmer s model .. versus pulse interrupts .. 8-43 Chapter 9 Memory Protection the MPU .. programmer s model .. access permissions .. aborts .. an MPU region .. and updating the MPU.

5 9-19 ContentsARM DDI 0337 GCopyright 2005-2008 ARM Limited. All rights AccessNon-ConfidentialChapter 10 Core core debug .. debug registers .. debug access example .. application registers in core debug .. 10-13 Chapter 11 System system debug .. debug access .. debug programmer s model .. 11-39 Chapter 12 Bus bus interfaces .. 3 compliance .. bus interface .. bus interface .. interface .. the code buses .. private peripheral interface .. alignment .. accesses that cross regions .. accesses .. buffer .. attributes .. timing characteristics .. 12-16 Chapter 13 Debug the DP .. 13-2 Chapter 14 Embedded Trace the ETM .. tracing.

6 Resources .. output .. architecture .. programmer s model .. 14-16 Chapter 15 Embedded Trace Macrocell the ETM interface .. ETM interface port descriptions .. status interface .. 15-6 ContentsviiiCopyright 2005-2008 ARM Limited. All rights DDI 0337 GNon-ConfidentialUnrestricted AccessChapter 16 AHB Trace Macrocell the AHB trace macrocell interface .. AHB trace macrocell interface port descriptions .. 16-3 Chapter 17 Trace Port Interface the TPIU .. registers .. wire output connection .. 17-21 Chapter 18 Instruction instruction timing .. instruction timings .. timings .. 18-7 Chapter 19AC timing parameters .. 19-2 Appendix ASignal .. interface.

7 Power interface .. interface .. interface .. bus interface .. Peripheral Bus interface .. interface .. interface .. interface .. Trace Macrocell interface .. interface .. interface .. A-18 Appendix BRevisionsGlossaryARM DDI 0337 GCopyright 2005-2008 ARM Limited. All rights AccessNon-ConfidentialList of TablesCortex-M3 Technical Reference ManualChange History .. iiTable 2-1 Application Program Status Register bit assignments .. 2-6 Table 2-2 Interrupt Program Status Register bit assignments .. 2-7 Table 2-3 Bit functions of the EPSR .. 2-8 Table 2-416-bit Cortex-M3 instruction summary .. 2-13 Table 2-532-bit Cortex-M3 instruction summary .. 2-16 Table 3-1 NVIC registers.

8 3-2 Table 3-2 Core debug registers .. 3-5 Table 3-3 Flash patch register summary .. 3-6 Table 3-4 DWT register summary .. 3-7 Table 3-5 ITM register summary .. 3-9 Table 3-6 AHB-AP register summary .. 3-10 Table 3-7 Summary of Debug interface port registers .. 3-10 Table 3-8 MPU registers .. 3-11 Table 3-9 TPIU registers .. 3-12 Table 3-10 ETM registers .. 3-13 Table 4-1 Memory interfaces .. 4-3 Table 4-2 Memory region permissions .. 4-4 Table 4-3 ROM table .. 4-7 Table 5-1 Exception types .. 5-4 Table 5-2 Priority-based actions of exceptions .. 5-6 Table 5-3 Priority grouping .. 5-8 Table 5-4 Exception entry steps .. 5-12 List of TablesxCopyright 2005-2008 ARM Limited.

9 All rights DDI 0337 GNon-ConfidentialUnrestricted AccessTable 5-5 Exception exit steps .. 5-17 Table 5-6 Exception return behavior .. 5-19 Table 5-7 Reset actions .. 5-20 Table 5-8 Reset boot-up behavior .. 5-21 Table 5-9 Transferring to exception processing .. 5-24 Table 5-10 Faults .. 5-28 Table 5-11 Debug faults .. 5-30 Table 5-12 Fault status and fault address registers .. 5-31 Table 5-13 Privilege and stack of different activation levels .. 5-32 Table 5-14 Exception transitions .. 5-32 Table 5-15 Exception subtype transitions .. 5-33 Table 6-1 Cortex-M3 processor clocks .. 6-2 Table 6-2 Cortex-M3 macrocell clocks .. 6-2 Table 6-3 Reset inputs .. 6-4 Table 6-4 Reset modes .. 6-5 Table 7-1 Supported sleep modes.

10 7-3 Table 8-1 NVIC registers .. 8-3 Table 8-2 Interrupt Controller Type Register bit assignments .. 8-8 Table 8-3 Auxiliary Control Register bit assignments .. 8-9 Table 8-4 SysTick Control and Status Register bit assignments .. 8-10 Table 8-5 SysTick Reload Value Register bit assignments .. 8-11 Table 8-6 SysTick Current Value Register bit assignments .. 8-12 Table 8-7 SysTick Calibration Value Register bit assignments .. 8-12 Table 8-8 Interrupt Set-Enable Register bit assignments .. 8-14 Table 8-9 Interrupt Clear-Enable Register bit assignments .. 8-14 Table 8-10 Interrupt Set-Pending Register bit assignments .. 8-15 Table 8-11 Interrupt Clear-Pending Registers bit assignments.