PM0056 Programming manual - STMicroelectronics

1 December 2017 DocID15491 Rev 61/1561PM0056 Programming manualSTM32F10xxx/20xxx/21xxx/L1xxxx Cortex -M3 Programming manualIntroductionThis Programming manual provides information for application and system-level software developers. It gives a full description of the STM32F10xxx/20xxx/21xxx/L1xxxx Cortex -M3 processor Programming model, instruction set and core STM32F10xxx/20xxx/21xxx/L1xxxx Cortex -M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: Outstanding processing performance combined with a fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Efficient processor core, system and memories Ultra-low-power consumption with integrated sleep modes Platform Rev 6 Contents1 About this document .. conventions .. of abbreviations for registers.

2 The STM32 Cortex -M3 processor and core peripherals .. level interface .. configurable debug .. -M3 processor features and benefits summary .. -M3 core peripherals .. 122 The Cortex -M3 processor .. model .. mode and privilege levels for software execution .. registers .. and interrupts .. types .. Cortex microcontroller software interface standard (CMSIS) .. model .. regions, types and attributes .. system ordering of memory accesses .. of memory accesses .. ordering of memory accesses .. endianness .. primitives .. hints for the synchronization primitives .. model .. states .. types .. handlers .. table .. priorities .. priority grouping .. entry and return .. 37 DocID15491 Rev 63 handling .. types .. escalation and hard faults .. status registers and fault address registers.

3 Management .. sleep mode .. from sleep mode .. external event input .. management Programming hints .. 433 The Cortex -M3 instruction set .. set summary .. functions .. the instruction descriptions .. when using PC or SP .. second operand .. operations .. alignment .. expressions .. execution .. width selection .. access instructions .. and STR, immediate offset .. and STR, register offset .. and STR, unprivileged .. , PC-relative .. and STM .. and POP .. and STREX .. data processing instructions .. , ADC, SUB, SBC, and RSB .. , ORR, EOR, BIC, and ORN .. 75 ContentsPM00564/156 DocID15491 Rev , LSL, LSR, ROR, and RRX .. and CMN .. and MVN .. , REV16, REVSH, and RBIT .. and TEQ .. and divide instructions .. , MLA, and MLS .. , UMLAL, SMULL, and SMLAL .. and UDIV.

4 Instructions .. and USAT .. instructions .. and BFI .. and UBFX .. and UXT .. and control instructions .. , BL, BX, and BLX .. and CBNZ .. and TBH .. instructions .. 1044 Core peripherals .. 105 DocID15491 Rev 65 the STM32 core peripherals .. protection unit (MPU) .. access permission attributes .. mismatch .. an MPU region .. design hints and tips .. type register (MPU_TYPER) .. control register (MPU_CR) .. region number register (MPU_RNR) .. region base address register (MPU_RBAR) .. region attribute and size register (MPU_RASR) .. vectored interrupt controller (NVIC) .. CMSIS mapping of the Cortex -M3 NVIC registers .. set-enable registers (NVIC_ISERx) .. clear-enable registers (NVIC_ICERx) .. set-pending registers (NVIC_ISPRx) .. clear-pending registers (NVIC_ICPRx).

5 Active bit registers (NVIC_IABRx) .. priority registers (NVIC_IPRx) .. trigger interrupt register (NVIC_STIR) .. and pulse interrupts .. design hints and tips .. register map .. control block (SCB) .. control register (SCB_ACTLR) .. base register (SCB_CPUID) .. control and state register (SCB_ICSR) .. table offset register (SCB_VTOR) .. interrupt and reset control register (SCB_AIRCR) .. control register (SCB_SCR) .. and control register (SCB_CCR) .. handler priority registers (SHPRx) .. handler control and state register (SCB_SHCSR) .. fault status register (SCB_CFSR) .. fault status register (SCB_HFSR) .. management fault address register (SCB_MMFAR) .. fault address register (SCB_BFAR) .. 147 ContentsPM00566/156 DocID15491 Rev control block design hints and tips .. register map.

6 Timer (STK) .. control and status register (STK_CTRL) .. reload value register (STK_LOAD) .. current value register (STK_VAL) .. calibration value register (STK_CALIB) .. design hints and tips .. register map .. 1545 Revision history .. 155 DocID15491 Rev 67/156PM0056 List of tables8 List of tablesTable of processor mode, execution privilege level, and stack use options.. 14 Table register set summary .. 15 Table register combinations .. 16 Table bit definitions .. 17 Table bit definitions .. 18 Table bit definitions .. 19 Table register bit definitions.. 20 Table register bit definitions .. 20 Table register bit assignments .. 21 Table register bit definitions .. 22 Table of memory accesses .. 25 Table access behavior .. 26 Table memory bit-banding regions .. 28 Table memory bit-banding regions .. 28 Table compiler intrinsic functions for exclusive access instructions.

7 31 Table of the different exception types .. 33 Table return behavior .. 39 Table .. 40 Table status and fault address registers .. 41 Table instructions .. 44 Table intrinsic functions to generate some Cortex-M3 instructions .. 49 Table intrinsic functions to access the special registers.. 50 Table code suffixes.. 57 Table access instructions .. 59 Table , pre-indexed and post-indexed offset ranges .. 62 Table offset ranges .. 66 Table processing instructions.. 72 Table and divide instructions .. 83 Table and unpacking instructions .. 88 Table and control instructions .. 91 Table ranges .. 92 Table instructions .. 97 Table core peripheral register regions .. 105 Table attributes summary .. 106 Table , C, B, and S encoding .. 107 Table policy for memory attribute encoding .. 107 Table encoding .. 108 Table region attributes for STM32.

8 111 Table SIZE field values .. 117 Table register map and reset values .. 117 Table of interrupts to the interrupt variables .. 119 Table bit assignments .. 125 Table functions for NVIC control .. 127 Table register map and reset values .. 128 Table grouping .. 135 Table fault handler priority fields .. 138 Table register map and reset value for STM32F2 and STM32L .. 148 Table register map and reset values .. 149 List of tablesPM00568/156 DocID15491 Rev 6 Table register map and reset values .. 154 Table revision history .. 155 DocID15491 Rev 69/156PM0056 List of figures9 List of figuresFigure Cortex-M3 implementation .. 11 Figure core registers .. 14 Figure , IPSR and EPSR bit assignments .. 16 Figure bit assignments .. 16 Figure bit assignments .. 20 Figure bit assignments .. 20 Figure bit assignments .. 21 Figure bit assignments.

9 21 Figure map .. 24 Figure mapping .. 29 Figure example .. 30 Figure table.. 35 Figure #3 .. 53 Figure #3 .. 53 Figure #3 .. 54 Figure #3 .. 54 Figure #3 .. 55 Figure example .. 110 Figure register mapping .. 125 Figure subregisters .. 142 About this documentPM005610/156 DocID15491 Rev 61 About this documentThis document provides the information required for application and system-level software development. It does not provide information on debug components, features, or material is for microcontroller software and hardware engineers, including those who have no experience of Arm Typographical conventionsThe typographical conventions used in this document are: List of abbreviations for registersThe following abbreviations are used in register descriptions: About the STM32 Cortex -M3 processor and core peripheralsThe Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications.

10 The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example:LDRSB<cond> <Rt>, [<Rn>, #<offset>]read/write (rw)Software can read and write to these (r)Software can only read these bits. write-only (w)Software can only write to this bit. Reading the bit returns the reset (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit (t)Software can only toggle this bit by writing 1.