RM0008 Reference manual - Keil

1 June 2009 Doc ID 13902 Rev 91/995RM0008 Reference manualSTM32F101xx, STM32F102xx, STM32F103xx, STM32F105xxand STM32F107xx advanced ARM-based 32-bit MCUsIntroductionThis Reference manual targets application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as STM32F10xxx throughout the document, unless otherwise STM32F10xxx is a family of microcontrollers with different memory sizes, packages and ordering information, mechanical and electrical device characteristics please refer to the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming information on the ARM Cortex -M3 core.

2 Please refer to the Cortex -M3 technical Reference documentsAvailable from : Cortex -M3 technical Reference manual , available from: from : STM32F101xx STM32F103xx datasheets STM32F10xxx Flash programming ContentsRM00082/995 Doc ID 13902 Rev 9 Contents1 Documentation conventions .. of abbreviations for registers .. availability .. 372 Memory and bus architecture .. architecture .. organization .. map .. SRAM .. banding .. Flash memory .. configuration .. 483 CRC calculation unit .. introduction .. main features .. functional description .. registers .. register (CRC_DR) .. data register (CRC_IDR) .. register (CRC_CR) .. register map .. 524 Power control (PWR).

3 Supplies .. A/D converter supply and Reference voltage .. backup domain .. regulator .. supply supervisor .. on reset (POR)/power down reset (PDR) .. voltage detector (PVD) .. modes .. 57RM0008 ContentsDoc ID 13902 Rev 93/995 down system clocks .. clock gating .. mode .. mode .. mode .. (AWU) from low-power mode .. control registers .. control register (PWR_CR) .. control/status register (PWR_CSR) .. register map .. 655 Backup registers (BKP) .. introduction .. main features .. functional description .. detection .. calibration .. registers .. data register x (BKP_DRx) (x = 1 ..42) .. clock calibration register (BKP_RTCCR).

4 Control register (BKP_CR) .. control/status register (BKP_CSR) .. register map .. 706 Low-, medium- and high-density reset and clock control (RCC) .. reset .. reset .. domain reset .. clock .. clock .. clock .. clock .. clock (SYSCLK) selection .. 81 ContentsRM00084/995 Doc ID 13902 Rev security system (CSS) .. clock .. clock .. capability .. registers .. control register (RCC_CR) .. configuration register (RCC_CFGR) .. interrupt register (RCC_CIR) .. peripheral reset register (RCC_APB2 RSTR) .. peripheral reset register (RCC_APB1 RSTR) .. peripheral clock enable register (RCC_AHBENR) .. peripheral clock enable register (RCC_APB2 ENR).

5 Peripheral clock enable register (RCC_APB1 ENR) .. domain control register (RCC_BDCR) .. register (RCC_CSR) .. register map .. 1027 Connectivity line devices: reset and clock control (RCC) .. reset .. reset .. domain reset .. clock .. clock .. clock .. clock .. clock (SYSCLK) selection .. security system (CSS) .. clock .. clock .. capability .. registers .. control register (RCC_CR) .. configuration register (RCC_CFGR) .. interrupt register (RCC_CIR) .. 118RM0008 ContentsDoc ID 13902 Rev 95/995 peripheral reset register (RCC_APB2 RSTR) .. peripheral reset register (RCC_APB1 RSTR) .. Peripheral Clock enable register (RCC_AHBENR) .. peripheral clock enable register (RCC_APB2 ENR).

6 Peripheral clock enable register (RCC_APB1 ENR) .. domain control register (RCC_BDCR) .. register (RCC_CSR) .. peripheral clock reset register (RCC_AHBRSTR) .. configuration register2 (RCC_CFGR2) .. register map .. 1368 General-purpose and alternate-function I/Os (GPIOs and AFIOs) .. functional description .. I/O (GPIO) .. bit set or reset .. interrupt/wakeup lines .. functions (AF) .. remapping of I/O alternate functions .. locking mechanism .. configuration .. configuration .. function configuration .. input configuration .. GPIO configurations .. registers .. configuration register low (GPIOx_CRL) (x= ) .. configuration register high (GPIOx_CRH) (x= ).

7 Input data register (GPIOx_IDR) (x= ) .. output data register (GPIOx_ODR) (x= ) .. bit set/reset register (GPIOx_BSRR) (x= ) .. bit reset register (GPIOx_BRR) (x= ) .. configuration lock register (GPIOx_LCKR) (x= ) .. function I/O and debug configuration (AFIO) .. OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 .. OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 .. alternate function remapping .. alternate function remapping .. 153 ContentsRM00086/995 Doc ID 13902 Rev alternate function remapping .. alternate function remapping .. alternate function remapping .. Alternate function remapping .. alternate function remapping .. alternate function remapping .. alternate function remapping.

8 Alternate function remapping .. registers .. control register (AFIO_EVCR) .. remap and debug I/O configuration register (AFIO_MAPR) .. interrupt configuration register 1 (AFIO_EXTICR1) .. interrupt configuration register 2 (AFIO_EXTICR2) .. interrupt configuration register 3 (AFIO_EXTICR3) .. interrupt configuration register 4 (AFIO_EXTICR4) .. and AFIO register maps .. 1679 Interrupts and events .. vectored interrupt controller (NVIC) .. calibration value register .. and exception vectors .. interrupt/event controller (EXTI) .. features .. diagram .. event management .. description .. interrupt/event line mapping .. registers .. mask register (EXTI_IMR) .. mask register (EXTI_EMR).

9 Trigger selection register (EXTI_RTSR) .. trigger selection register (EXTI_FTSR) .. interrupt event register (EXTI_SWIER) .. register (EXTI_PR) .. register map .. 18110 DMA controller (DMA) .. 182RM0008 ContentsDoc ID 13902 Rev 97/995 introduction .. main features .. functional description .. transactions .. channels .. data width, data alignment and endians .. management .. request mapping .. registers .. interrupt status register (DMA_ISR) .. interrupt flag clear register (DMA_IFCR) .. channel x configuration register (DMA_CCRx) (x = 1 ..7) .. channel x number of data register (DMA_CNDTRx) (x = 1 ..7) . channel x peripheral address register (DMA_CPARx) (x = 1.)

10 7) channel x memory address register (DMA_CMARx) (x = 1 ..7) . register map .. 19611 Analog-to-digital converter (ADC) .. introduction .. main features .. functional description .. on-off control .. clock .. selection .. conversion mode .. conversion mode .. diagram .. watchdog .. mode .. channel management .. Discontinuous mode .. alignment .. programmable sample time .. 207 ContentsRM00088/995 Doc ID 13902 Rev on external trigger .. request .. ADC mode .. simultaneous mode .. simultaneous mode .. interleaved mode .. interleaved mode .. trigger mode .. mode .. regular/injected simultaneous mode .. regular simultaneous + alternate trigger mode.