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1 R ge1999 PCIBus SolutionsData ManualPrinted in , 12/99 SCPS051 PCI2250 PCI-to-PCI BridgeData ManualLiterature Number: SCPS051 December 1999 Printed on Recycled PaperIMPORTANT NOTICET exas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of warrants performance of its semiconductor products to the specifications applicable at thetime of sale in accordance with TI s standard warranty. Testing and other quality controltechniques are utilized to the extent TI deems necessary to support this warranty.

2 Specific testingof all parameters of each device is not necessarily performed, except those mandated bygovernment APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVEPOTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY ORENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTORPRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FORUSE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLYAT THE CUSTOMER S order to minimize risks associated with the customer s applications, adequate design andoperating safeguards must be provided by the customer to minimize inherent or assumes no liability for applications assistance or customer product design. TI does notwarrant or represent that any license, either express or implied, is granted under any patent right,copyright, mask work right, or other intellectual property right of TI covering or relating to anycombination, machine, or process in which such semiconductor products or services might beor are used.

3 TI s publication of information regarding any third party s products or services doesnot constitute TI s approval, warranty or endorsement 1999, Texas Instruments IncorporatediiiContentsSectionTitlePage1 Introduction1 1.. 1.. 1.. Documents1 2.. Information1 2.. 2 Terminal Descriptions2 1.. 3 Feature/Protocol Descriptions3 1.. to the PCI22503 1.. Commands3 2.. Cycles3 2.. Cycle Generation3 4.. Clocks3 4.. Arbitration3 5.. Bus Arbitration3 5.. Secondary Bus Arbitration3 5.. Secondary Bus Arbitration3 6.. Options3 6.. Windows With Programmable Decoding3 6.. Error Handling3 6.. Write Parity Error3 7.. Write Timeout3 7.. Abort on Posted Writes3 7.. Abort on Posted Writes3 7.. Delayed Write Timeout3 7.. Delayed Read Timeout3 7.. SERR3 7.. Handling and Parity Error Reporting3 7.. Parity Error3 7.. Parity Error3 8.

4 And Target Abort Handling3 8.. Timer3 8.. Transactions3 8.. Pins3 9.. PCI Hot Swap Support3 9.. Clock Run Feature3 10.. Power Management3 10.. in Low Power States3 10.. iv4 Bridge Configuration Header4 1.. ID Register4 2.. ID Register4 2.. Register4 3.. Register4 4.. ID Register4 5.. Code Register4 5.. Line Size Register4 5.. Latency Timer Register4 6.. Type Register4 6.. Register4 6.. Address Register 04 7.. Address Register 14 7.. Bus Number Register4 7.. Bus Number Register4 8.. Bus Number Register4 8.. Bus Latency Timer Register4 8.. Base Register4 9.. Limit Register4 9.. Status Register4 10.. Base Register4 11.. Limit Register4 11.. Memory Base Register4 11.. Memory Limit Register4 12.. Base Upper 32 Bits Register4 12.. Limit Upper 32 Bits Register4 12.. Base Upper 16 Bits Register4 13.

5 Limit Upper 16 Bits Register4 13.. Pointer Register4 13.. ROM Base Address Register4 14.. Line Register4 14.. Pin Register4 14.. Control Register4 15.. 5 Extension Registers5 1.. Control Register5 1.. Diagnostic Register5 2.. Control Register5 3.. Window Base 0, 1 Registers5 4.. Window Limit 0, 1 Registers5 4.. Window Enable Register5 5.. Window Map Register5 5.. Decode Control Register5 6.. Decode Control Register5 7.. Decode Enable Register5 8.. Control Register5 9.. Decode Map Register5 10.. Run Control Register5 11.. Control Register5 11.. Status Register5 13.. Request Mask Register5 14.. Timeout Status Register5 15.. Event Disable Register5 16.. Clock Control Register5 17.. Status Register5 18.. Capability ID Register 5 18.. Next Item Pointer Register5 19.. Management Capabilities Register5 19.

6 Management Control/Status Register5 20.. Bridge Support Register5 21.. Register5 21.. Capability ID Register5 22.. Next Item Pointer Register5 22.. Swap Control Status Register5 23.. 6 Electrical Characteristics6 1.. Maximum Ratings Over Operating Temperature Ranges6 1. Operating Conditions6 2.. Operating Conditions for PCI Interface6 2.. Characteristics Over Recommended Operating Conditions 6 Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature6 4.. Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature6 5.. Measurement Information6 6.. Bus Parameter Measurement Information6 7.. 7 Mechanical Data7 1.. viList of IllustrationsFigureTitlePage2 1 PCI2250 PGF LQFP Terminal Diagram2 1.. 2 2 PCI2250 PCM PQFP Terminal Diagram2 2.

7 3 1 System Block Diagram3 1.. 3 2 PCI AD31 AD0 During Address Phase of a Type 0 Configuration Cycle3 23 3 PCI AD31 AD0 During Address Phase of a Type 1 Configuration Cycle3 33 4 Bus Hierarchy and Numbering3 4.. 3 5 Secondary Clock Block Diagram3 5.. 6 1 Load Circuit and Voltage Waveforms6 6.. 6 2 PCLK Timing Waveform6 7.. 6 3 RSTIN Timing Waveforms6 7.. 6 4 Shared-Signals Timing Waveforms6 7.. viiList of TablesTableTitlePage2 1 PGF LQFP Signal Names Sorted by Terminal Number2 3.. 2 2 PCM LQFP Signals Sorted by Terminal Number2 4.. 2 3 Signal Names Sorted Alphabetically to PGF Terminal Number2 5.. 2 4 Signal Names Sorted Alphabetically to PCM Terminal Number2 6.. 2 5 Primary PCI System2 7.. 2 6 Primary PCI Address and Data2 7.. 2 7 Primary PCI Interface Control2 8.. 2 8 Secondary PCI System2 9.. 2 9 Secondary PCI Address and Data2 10.. 2 10 Secondary PCI Interface Control2 11.

8 2 11 Miscellaneous Terminals2 12.. 2 12 Power Supply2 12.. 3 1 PCI Command Definition3 2.. 4 1 Bridge Configuration Header4 1.. 4 2 Bit Field Access Tag Descriptions4 2.. 4 3 Command Register4 3.. 4 4 Status Register4 4.. 4 5 Secondary Status Register4 10.. 4 6 Bridge Control Register4 15.. 5 1 Chip Control Register5 1.. 5 2 Extended Diagnostic Register5 2.. 5 3 Arbiter Control Register5 3.. 5 4 Extension Window Enable Register5 5.. 5 5 Extension Window Map Register5 5.. 5 6 Secondary Decode Control Register5 6.. 5 7 Primary Decode Control Register5 7.. 5 8 Port Decode Enable Register5 8.. 5 9 Buffer Control Register5 9.. 5 10 Port Decode Map Register5 10.. 5 11 Clock Run Control Register5 11.. 5 12 Diagnostic Control Register5 12.. 5 13 Diagnostic Status Register5 13.. 5 14 Arbiter Request Mask Register5 14.. 5 15 Arbiter Timeout Status Register5 15.

9 5 16 P_SERR Event Disable Register5 16.. 5 17 Secondary Clock Control Register5 17.. 5 18 P_SERR Status Register5 18.. viii5 19 Power Management Capabilities Register5 19.. 5 20 Power Management Capabilities Register5 20.. 5 21 PMCSR Bridge Support Register5 21.. 5 22 Hot Swap Control Status Register5 23.. 1 11 DescriptionThe Texas Instruments PCI2250 PCI-to-PCI bridge provides a high performance connection path between twoperipheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targetson another PCI bus, and the PCI2250 allows bridged transactions to occur concurrently on both buses. The bridgesupports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge PCI2250 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electricalloading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses.

10 ThePCI2250 provides two-tier internal arbitration for up to four secondary bus masters and may be implemented withan external secondary PCI bus PCI2250 provides compact-PCI (CPCI) hot-swap extended capability, which makes it an ideal solution formultifunction compact-PCI cards and adapting single function cards to hot-swap PCI2250 bridge is compliant with the PCI-to-PCI Bridge Specification. It can be configured for positive decodingor subtractive decoding on the primary interface, and provides several additional decode options that make it an idealbridge to custom PCI applications. Two extension windows are included, and the PCI2250 provides decoding of serialand parallel port PCI2250 is compliant with PCI Power Management Interface Specification Revisions and Also, thePCI2250 offers PCI CLKRUN bridging support for low-power mobile and docking applications.