DLPC3430 and DLPC3435 Display Controller …

1 Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design DLPC3430 , DLPC3435 . DLPS038C JULY 2014 REVISED JULY 2016. DLPC3430 and DLPC3435 Display Controller 1 Features 2 Applications 1 Display Controller for DLP2010 (.2 WVGA) TRP Embedded Projection: DMD Smart Phone Supports Input Image Sizes up to 720p Tablet Low-Power DMD Interface With Interface Camera Training Camcorder Input frame rates up to 120Hz for 2D and 3D Laptop 24-Bit, Input Pixel Interface Support: Battery-Powered Mobile Accessory Parallel or BT656, Interface Protocols Wearable (Near-Eye) Display Pixel Clock up to 150 MHz Interactive Display Multiple Input Pixel Data Format Options Low-Latency Gaming Display Supports Landscape and Potrait Inputs Digital Signage MIPI DSI Interface Type 3 (only supported with DLPC3430 ) 3 Description 1-4 lanes, up to 470 Mbps lane speed The DLPC3430 and DLPC3435 digital Controller , part Pixel Data Processing: of the DLP2010 (.)

2 2 WVGA) chipset, support reliable operation of the DLP2010 digital micromirror device IntelliBright Suite of Image Processing (DMD). The DLPC3430 and DLCP3435 controllers Algorithms provide a convenient, multi-functional interface Content Adaptive Illumination Control between user electronics and the DMD, enabling Local Area Brightness Boost small form factor and low power Display applications. Image Resizing (Scaling) Device Information(1)(2). 1D Keystone Correction PART NUMBER PACKAGE BODY SIZE (NOM). Color Coordinate Adjustment DLPC3430 NFBGA (176) mm2. Active Power Management Processing DLPC3435 NFBGA (201) mm2. Programmable Degamma (1) For all available packages, see the orderable addendum at Color Space Conversion the end of the data sheet. (2) DSI is available for the DLPC3430 only. DSI is not available 4:2:2 to 4:4:4 Chroma Interpolation for the DLPC3435 .

3 Field Scaled De-Interlacing Two Package Options: Typical Standalone System 176-Pin, 7- 7-mm, Pitch, NFBGA. 201-Pin, 13- 13-mm, Pitch, NFBGA. External Flash Support Auto DMD Parking at Power Down Embedded Frame Memory (eDRAM). System Features: I2C Control of Device Configuration Programmable Splash Screens Programmable LED Current Control Display Image Rotation One Frame Latency 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLPC3430 , DLPC3435 . DLPS038C JULY 2014 REVISED JULY 2016 Table of Contents 1 Features .. 1 Overview .. 30. 2 Applications .. 1 Functional Block Diagram .. 30. 3 Description .. 1 Feature 31. Device Functional 42. 4 Revision 2. 5 Pin Configuration and Functions.

4 3 9 Application and Implementation .. 43. Application 43. 6 14. Typical Application .. 43. Absolute Maximum Ratings .. 14. ESD 14 10 Power Supply Recommendations .. 45. System Power-Up and Power-Down Sequence .. 45. Recommended Operating 15. DLPC343x Power-Up Initialization 48. Thermal Information .. 15. DMD Fast PARK Control (PARKZ) .. 48. Electrical Characteristics over Recommended Operating Conditions .. 16 Hot Plug Usage .. 48. Electrical 17 Maximum Signal Transition 48. Internal Pullup and Pulldown 19 11 49. High-Speed Sub-LVDS Electrical 19 Layout Guidelines .. 49. Low-Speed SDR Electrical 20 Layout Example .. 54. System Oscillators Timing Requirements .. 21 12 Device and Documentation Support .. 55. Power-Up and Reset Timing Requirements .. 21 Device Support .. 55. Parallel Interface Frame Timing Requirements .. 22 Related Links.

5 57. Parallel Interface General Timing Requirements .. 23 Community 57. BT656 Interface General Timing Requirements .. 24 Trademarks .. 57. DSI Host Timing Requirements .. 24 Electrostatic Discharge Caution .. 57. Flash Interface Timing Requirements .. 25 Glossary .. 57. 7 Parameter Measurement Information .. 26 13 Mechanical, Packaging, and Orderable HOST_IRQ Usage Model .. 26 Information .. 57. Input 27 Package Option Addendum .. 58. 8 Detailed Description .. 30. 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2016) to Revision C Page Added DSI pin functions inTable 1 .. 7. Removed GPIO_07 LED Enable features .. 10. Added DSI Host Timing Requirements .. 24. Updated Input 27. Added DSI Interface - Supported Data Transfer Formats.

6 29. Added Display Serial Interface DSI .. 31. Added 3-D Glasses 38. Added PCB Layout Guidelines for DSI 51. Changes from Revision A (January 2016) to Revision B Page Updated data sheet throughout to show the correct information for the DLPC3430 and DLPC3435 controllers and corrected part numbers in text and images to show DLPC3430 and DLPC3435 .. 1. Changes from Original (July 2014) to Revision A Page Updated Device Markings image and 55. 2 Submit Documentation Feedback Copyright 2014 2016, Texas Instruments Incorporated Product Folder Links: DLPC3430 DLPC3435 . DLPC3430 , DLPC3435 . DLPS038C JULY 2014 REVISED JULY 2016. 5 Pin Configuration and Functions ZVB Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15. 176-Pin NFBGA A. DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W. LK DATA DATAH_P DATAG_P DATAF_P DATAE_P P DATAD_P DATAC_P DATAB_P DATAA_P.

7 CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM. Bottom View B. DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W. ARSTZ DATA DATAH_N DATAG_N DATAF_N DATAE_N N DATAD_N DATAC_N DATAB_N DATAA_N. SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0. HWTEST_E. C DD3P DD3N VDDLP12 VSS VDD VSS VCC VSS VCC. N. RESETZ SPI0_CSZ1 PARKZ GPIO_00 GPIO_01. D DD2P DD2N VDD VCC VDD VSS VDD VSS VDD VSS VCC_FLSH VDD VDD GPIO_02 GPIO_03. E DCLKP DCLKN VDD VSS VCC VSS GPIO_04 GPIO_05. F DD1P DD1N RREF VSS VCC VDD GPIO_06 GPIO_07. G DD0P DD0N VSS_PLLM VSS VSS VSS GPIO_08 GPIO_09. PLL_REFCL. H K_I. VDD_PLLM VSS_PLLD VSS VSS VDD GPIO_10 GPIO_11. PLL_REFCL. J K_O. VDD_PLLD VSS VDD VDD VSS GPIO_12 GPIO_13. K PDATA_1 PDATA_0 VDD VSS VSS VCC GPIO_14 GPIO_15. L PDATA_3 PDATA_2 VSS VDD VDD VDD GPIO_16 GPIO_17. M PDATA_5 PDATA_4 VCC_INTF VSS VSS VDD VCC_INTF VSS VDD VDD VCC VSS JTAGTMS1 GPIO_18 GPIO_19.

8 PDM_CVS_. N PDATA_7 PDATA_6 VCC_INTF. TE. HSYNC_CS 3DR VCC_INTF HOST_IRQ IIC0_SDA IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1 TSTPT_6 TSTPT_7. DATEN_CM. P VSYNC_WE. D. PCLK PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK JTAGTDI TSTPT_4 TSTPT_5. R PDATA_8 PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22 IIC1_SDA IIC1_SCL TSTPT_0 TSTPT_1 TSTPT_2 TSTPT_3. ZEZ Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15. 201-Pin NFBGA A. DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W. LK DATA DATAH_P DATAG_P DATAF_P DATAE_P P DATAD_P DATAC_P DATAB_P DATAA_P. CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM. Bottom View B. DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W. ARSTZ DATA DATAH_N DATAG_N DATAF_N DATAE_N N DATAD_N DATAC_N DATAB_N DATAA_N.

9 SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0. HWTEST_E. C DD3P DD3N VDDLP12 VSS VDD VSS VCC VSS VCC. N. RESETZ SPI0_CSZ1 PARKZ GPIO_00 GPIO_01. D DD2P DD2N VDD VCC VDD VSS VDD VSS VDD VSS VCC_FLSH VDD VDD GPIO_02 GPIO_03. E DCLKP DCLKN VDD VSS VCC VSS GPIO_04 GPIO_05. F DD1P DD1N RREF VSS VSS VSS VSS VSS VSS VCC VDD GPIO_06 GPIO_07. G DD0P DD0N VSS_PLLM VSS VSS VSS VSS VSS VSS VSS VSS GPIO_08 GPIO_09. PLL_REFCL. H K_I. VDD_PLLM VSS_PLLD VSS VSS VSS VSS VSS VSS VSS VDD GPIO_10 GPIO_11. PLL_REFCL. J K_O. VDD_PLLD VSS VDD VSS VSS VSS VSS VSS VDD VSS GPIO_12 GPIO_13. K PDATA_1 PDATA_0 VDD VSS VSS VSS VSS VSS VSS VSS VCC GPIO_14 GPIO_15. L PDATA_3 PDATA_2 VSS VDD VDD VDD GPIO_16 GPIO_17. M PDATA_5 PDATA_4 VCC_INTF VSS VSS VDD VCC_INTF VSS VDD VDD VCC VSS JTAGTMS1 GPIO_18 GPIO_19. PDM_CVS_. N PDATA_7 PDATA_6 VCC_INTF. TE. HSYNC_CS 3DR VCC_INTF HOST_IRQ IIC0_SDA IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1 TSTPT_6 TSTPT_7.

10 DATEN_CM. P VSYNC_WE. D. PCLK PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK JTAGTDI TSTPT_4 TSTPT_5. R PDATA_8 PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22 IIC1_SDA IIC1_SCL TSTPT_0 TSTPT_1 TSTPT_2 TSTPT_3. Copyright 2014 2016, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: DLPC3430 DLPC3435 . DLPC3430 , DLPC3435 . DLPS038C JULY 2014 REVISED JULY 2016 Pin Functions Board Level Test, Debug, and Initialization PIN. I/O DESCRIPTION. NAME NUMBER. Manufacturing test enable signal. This signal should be connected directly to ground on the HWTEST_EN C10 I6. PCB for normal operation. DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to enable normal operation. PARKZ should be set high prior to releasing RESETZ (that is, prior to the low-to-high transition on the RESETZ input).