DM385 and DM388 DaVinci Digital Media Processor …

1 DM385 , MARCH2013 REVISEDDECEMBER2013DM385and DM388 DaVinci DigitalMediaProcessorCheckfor Samples: DM385 , DM3881 High-PerformanceSystem-on-Chip(SoC) High-PerformanceDaVinciDigitalMedia ProgrammableHigh-DefinitionVideoImagePro cessorsCoprocessing(HDVICPv2) Engine Up to 1000-MHzARM Cortex -A8 RISC Encode,Decode,TranscodeOperationsProcess or ,MPEG-2,VC-1,MPEG-4 Up to 2000 ARMC ortex-A8 MIPSSP/ASP,JPEG/MJPEG ARMC ortex-A8 Core Fourth-GenerationMotion-CompensatedNoise Filter( DM388 Only) ARMv7 Architecture MediaController In-Order,Dual-Issue,SuperscalarProcessor Core Controlsthe HDVPSS,HDVICP2,and ISS NEON MultimediaArchitecture Endianness SupportsIntegerand FloatingPoint ARMI nstructionsand Data LittleEndian Jazelle RCTE xecutionEnvironment HD VideoProcessingSubsystem(HDVPSS) ARMC ortex-A8 MemoryArchitecture Two165-MHzHD VideoCaptureInputs 32 KBof Instructionand DataCaches One16- or 24-BitInput,SplittableIntoDual8-BitSD CapturePorts 256 KBof L2 CachewithECC One8-, 16-, or 24-BitHD Inputand 8-Bit 64 KBof RAM,48 KBof BootROMSD InputCapturePort 256 KBof On-ChipMemoryController(OCMC) Two165-MHzHD VideoDisplayOutputsRAM One16-, 24-, or 30-Bitand One16- or 24- ImagingSubsystem(ISS)Bit Output CameraSensorConnection ComponentHD AnalogOutput ParallelConnectionfor Raw(up to 16-Bit) CompositeAnalogOutputand (8- or 16-Bit) TransmitterwithIntegrated CSI2 SerialConnectionPHY ImageSensorInterface(ISIF)for Handling AdvancedVideoProcessingFeaturesSuchImage and VideoDataFromthe Cameraas Scan,Format,and RateConversionSensor ThreeGraphicsLayersand Compositors ImagePipeInterface(IPIPEIF)

2 For ImageandVideoDataConnectionBetweenCamera 32-BitDDR2,DDR3,and DDR3 LSDRAMS ensor,ISIF,IPIPE,and DRAMI nterface ImagePipe(IPIPE)for Real-TimeImageand Supportsup to 400 MHzfor DDR2,533 MHzVideoProcessingfor DDR3,and 533 MHzfor DDR3L Resizer Up to Twox 16 Devices,2 GBof TotalAddressSpace ResizingImageand VideoFrom1/16xto8x DynamicMemoryManager(DMM) GeneratingTwoDifferentResizing ProgrammableMulti-ZoneMemoryOutputsConcu rrentlyMapping Hardware3A Engine(H3A)for Generating EnablesEfficient2D BlockAccessesKey Statisticsfor 3A (AE,AWB,and AF) SupportsTiledObjectsin 0 , 90 , 180 , orControl270 Orientationand Mirroring FaceDetect(FD)Engine HardwareFaceDetectionfor up to 35 FacesPer Frame1 Pleasebe awarethat an importantnoticeconcerningavailability,st andardwarranty,and use in criticalapplicationsofTexasInstrumentsse miconductorproductsand disclaimerstheretoappearsat the end of this ,XDSare trademarksof a trademarkof othertrademarksare the propertyof currentas of 2013,TexasInstrumentsIncorporatedspecifi cationsper the termsof the necessarilyincludetestingof all , DM388 SPRS821D MARCH2013 General-PurposeMemoryController(GPMC) FourInter-IntegratedCircuit(I2C Bus ) Ports 8- or 16-BitMultiplexedAddressand Data TwoMultichannelAudioSerialPorts(McASP)Bu s Six SerializerTransmitand ReceivePorts 512 MBof TotalAddressSpaceDivided TwoSerializerTransmitand ReceivePortsAmongup to 8 ChipSelects DIT-CapableFor S/PDIF(All Ports) GluelessInterfaceto NORF lash,NAND FourAudioTrackingLogic(ATL)

3 ModulesFlash(BCH/HammingErrorCodeDetecti on), Real-TimeClock(RTC)SRAMand Pseudo-SRAM One-Timeor PeriodicInterruptGeneration ErrorLocatorModule(ELM)Outsideof Up to 125 General-PurposeI/O (GPIO)PinsGPMCto Provideup to 16-Bitor 512-Byte OneSpinLockModulewithup to 128 HardwareHardwareECCfor NANDS emaphores FlexibleAsynchronousProtocolControlfor OneMailboxModulewith12 MailboxesInterfaceto FPGA,CPLD,ASICs,and More On-ChipARMROMB ootloader(RBL) EnhancedDirectMemoryAccess(EDMA) Power,Reset,and ClockManagementController SmartReflex Technology(Level2b) FourTransferControllers MultipleIndependentCorePowerDomains 64 IndependentDMAC hannels MultipleIndependentCoreVoltageDomains 8 QDMAC hannels Supportfor MultipleOperatingPointsper EthernetSwitchwithDual10-, 100-,orVoltageDomain1000-MbpsExternalInt erfaces(EMACS oftware) ClockEnableand DisableControlforSubsystemsand Peripherals ( Only) 32 KBof EmbeddedTraceBuffer (ETB ) and MII/RMII/GMII/RGMIIM ediaIndependent5-pinTraceInterfacefor DebugInterfaces (JTAG)Compatible ManagementDataI/O (MDIO)Module 609-PinPb-FreeBGAP ackage(AARS uffix), Channel IEEE1588 Time-Stampingand IndustrialTechnologyto ReducePCBCost( ) PortswithIntegratedPHYs 45-nmCMOST echnology Full-SpeedClients and General ,Full-,and Low-SpeedHostsI/O SupportsEnd Points0-15 OnePCI PortwithIntegratedPHY Supportedon All DM385 Devices DM388 DeviceswithPCIeEnabled SinglePortwith1 Laneat GT/s Configurableas RootComplexor Endpoint Eight32-BitGeneral-PurposeTimers(Timer1 8) OneSystemWatchdogTimer(WDT0) ThreeConfigurableUART/IrDA/CIRM odules UART0withModemControlSignals Supportsup to SIR,MIR,FIR ( MBAUD)

4 ,and CIR FourSerialPeripheralInterfaces(SPIs)(up to48 MHz) EachwithFourChipSelects ThreeMMC/SD/SDIOS erialInterfaces(up to48 MHz) Supportingup to 1-, 4-, or 8-BitModes2 High-PerformanceSystem-on-Chip(SoC)Copyr ight 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLinks:D M385DM388DM385, MARCH2013 IP Netcam VideoIP Phones EmbeddedUSBE ncodingCameras All CameraApplications HD VideoConferencing- Skype Endpoints DigitalSignage MediaPlayersand Adapters MobileMedicalImaging NetworkProjectors HomeAudioand VideoEquipment EmbeddedVision PortableMedicalImagingand Diagnosticsand PatientMonitoring RemoteMediaDisplay ThinClients Camcorders DigitalScanner VideoDoorbells DigitalPhotoFrames IntrusionControlPanelswithVideo AccessControlPanelswithVideoCopyright 2013,TexasInstrumentsIncorporatedHigh-Pe rformanceSystem-on-Chip(SoC)3 SubmitDocumentationFeedbackProductFolder Links.

5 DM385DM388DM385, DM388 SPRS821D MARCH2013 DM388 DaVinciDigitalMediaProcessorsare a highlyintegrated,cost-effective,low-powe r,programmableplatformthat leveragesTI s DaVinciprocessortechnologyto meetthe processingneedsofHD VideoConferencing- Skypeendpoints,IP Netcam,DigitalSignage,MediaPlayersand Adapters,MobileMedicalImaging,NetworkPro jectors,HomeAudioand VideoEquipment,and similardevicesinSD, HD,and 4K x 2K thedevicesupports1080p60of real the lowestpossiblebit rateunderallconditions,reducingvaluables toragespaceto a addition,the devicealsosupportsothervideocodecssuchas MJPEG,MPEG-2, full set of videopreprocessingand postprocessingfunctionsto ensurethe best low powerconsumptionand high performanceof the devicemakesit particularlysuitablefor portableand DM388is uniquelycapableof runningthe Fourth-GenerationMotion-CompensatedNoise Filteringtechnologyof deviceenablesoriginal-equipmentmanufactu rers(OEMs)and original-designmanufacturers(ODMs)to quicklybringto marketdevicesfeaturingrobustoperatingsys temssupport,rich userinterfaces,andhighprocessingperforma ncethroughthe maximumflexibilityof a devicealsocombinesprogrammablevideoand audioprocessingwith a deviceprocessorsincludea high-definitionvideoand imagingcoprocessor2 (HDVICP2)

6 ,to off-loadmanyvideoand imagingprocessingtasksfor commonvideoand an ARMC ortex-A8 RISCCPU with NEON extensionand high-definitionvideoand ARMlets developersseparatecontrolfunctionsfromA/ V algorithmsprogrammedoncoprocessors,thusr educingthe complexityof the ARMC ortex-A832-bitRISC processorwith NEON floating-pointextensionincludes:32 KBof instructioncache;32 KBof datacache;256 KBof L2 cachewith ECC;48 KBof bootROM;and 64 KBof rich peripheralset providesthe abilityto controlexternalperipheraldevicesand detailson eachperipheral,see the relatedsectionsin this documentand peripheralset includes:HD VideoProcessingSubsystem;Dual-PortGigabi tEthernetMACs(10/100/1000 Mbps)(EthernetSwitch)withMII/RMII/GMII/R GMIIandMDIO interfacesupportingIEEE1588 Time-Stamping,and IndustrialEthernetProtocols;two USBportswith PHY;PCIex1 GEN2-Compliantinterface;two serializerMcASPaudioserialports(withDIT mode);threeUART swith IrDAand CIR support;four SPI serialinterfaces;a CSI2serialconnection;threeMMC/SD/SDIO serialinterfaces;four I2C masterand slaveinterfaces;a parallelcamerainterface(CAM);up to 125 general-purposeI/Os(GPIOs);eight32-bitge neral-purposetimers;systemwatchdogtimer; DDR2/DDR3/DDR3 LSDRAM interface;flexible8- or 16-bitasynchronousmemoryinterface;a SpinLock.

7 And ,TI providesa completeset of developmenttoolsfor the ARMwhichincludeC compilersanda Microsoft Windows debuggerinterfacefor visibilityinto (SoC)Copyright 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLinks:D M385DM388 System InterconnectSerial InterfacesProgram/Data StorageConnectivity256 KB On-Chip RAMARM Subsystem32 KBD-Cache256 KB L2 Cachewith ECCNEONFPUC ortex -A8 CPUTMICE CrusherRAM64 KBBoot ROM48 KB32 KBI-CacheImagingSubsystemResizerParallel Cam InputVideo ProcessingSubsystemVideo CaptureDisplay ProcessingHD OSDSD OSDHD VENCSD VENCHDMI XmtSD DACHD DAC (3)MDIOPCIe (One x1 Port)(2)EMAC(R)(G)MII(2)USB (2)EDMAGPMC+ELMMMC/SD/SDIO(3)DDR2/332-bi tMcASP(2)SPI (4)UART (3)I C (4)2 System ControlReal-TimeClockPRCMGP Timer (8)JTAGW atchdogTimerMailboxSpinlockCSI2 Serial InputIPIPEH3 AMedia Controller SubsystemHigh Definition Video ImageCoprocessor (HDVICP)Face Detect (FD)PeripheralsMiscellaneousGPIO (4)Noise Filtering Engine(1) DM385 , MARCH2013 showsthe functionalblockdiagramof the device.

8 (1)NoiseFilteringEngineis availableonly on DM388 .(2)PCIeis supportedon all DM385devicesand also on DM388deviceswith FunctionalBlockDiagramCopyright 2013,TexasInstrumentsIncorporatedHigh-Pe rformanceSystem-on-Chip(SoC)5 SubmitDocumentationFeedbackProductFolder Links:DM385DM388DM385, DM388 SPRS821D MARCH2013 High-PerformanceSystem-on-Chip(SoC).. PeripheralInformationand (ATL).. Cortex -A8 MicroprocessorUnit( Processor ) (EMACSW).. (GPIO).. (GPMC) (FD) (ELM).. (HDMI).. (HDVPSS)..2013 (I2C).. (ISS).. (McASP)..2514 (MMC/SD/SDIO).. (PCIe).. (SPI).. (UART)..2696 ( ).. Deviceand SupplyVoltageand OperatingTemperature(UnlessOtherwiseNote d)..12710 Power,Reset,Clocking,and the ,Resetand ClockManagement(PRCM) 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLinks:D M385DM388DM385, MARCH2013 REVISEDDECEMBER2013 RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the revisionhistoryhighlightsthe technicalchangesmadeto the documentin the all DM385devicesand also on DM388deviceswith PCIeenabledto: ,Features Figure1-1,FunctionalBlockDiagram ,PCI Express(PCIe)TerminalFunctions Table4-10,PinsUsedin PCIeBootmode ,PeripheralComponentInterconnectExpress( PCIe) Figure9-1,DeviceNomenclatureAddedsupport for 4K x 2K resolution: ,Description ,HDVICP2 Overview ,ImagingSubsystem(ISS)Addednotesspecifyi ngOPP100is supportedonly on DM388commercialtemperaturedevicesto.

9 ,RecommendedOperatingConditions ,ReliabilityData ,DynamicVoltageFrequencyScaling Table7-3,DeviceOperatingPoints(OPPs) Table7-4,SupportedOPPC ombinationsPower,Reset,ChangedOPP100spee dfrom500 to 600 MHzfor ARMC ortex-A8in Table7-3,DeviceOperatingPointsClocking,a nd(OPPs).InterruptsRemovedrequirementtha t the maximumvoltagedifferencebetweenCVDDand any otherCVDD_xvoltagedomainmustbe < 150 mV. Table7-4,SupportedOPPC ombinationsCopyright 2013,TexasInstrumentsIncorporatedContent s7 SubmitDocumentationFeedbackProductFolder Links:DM385DM388DM385, DM388 SPRS821D MARCH2013 showsa comparisonbetweendevices,highlightingthe providesan overviewof the DM385and DM388 DaVinci DigitalMediaProcessors,,whichincludessig nificantfeaturesof the device,includingthe capacityof on-chipRAM,peripherals,and thepackagetype with pin Characteristicsof the ProcessorHARDWAREFEATURESDM385/DM3881 16-/24-bitHD CapturePortor2 8-bitSD CapturePortsand1 8/16/24-bitHD InputPortand1 8-bitSD InputPortandHD VideoProcessingSubsystem(HDVPSS)1 16-/24-/30-bitHD DisplayPortor 1 Transmitterand1 16-/24-bitHD DisplayPortand1 SD VideoDACand3 HD VideoDACs1 ParallelCameraInputfor Raw(up to 16-bit)ImagingSubsystem(ISS)and (8/16-bit)and 1 CSI2 SerialInputDDR2/3 MemoryController16-/32-bitBus WidthAsynchronous(8-/16-bitbus width)

10 GPMC+ ELMRAM,NOR,NAND64 IndependentChannelsEDMA8 QDMAC hannels10/100/1000 EthernetMACS witchwith ManagementData1 (with2 MII/RMII/GMII/RGMII)Input/Output(MDIO)2 (SupportsHigh-and Full-Speedas ,Full-,and Low-Speedas a Host)PCI Port ( GT/slane)Not all peripheralspins are availableat8 (32-bitGeneralpurpose)the sametime (forTimersandmoredetails,see the1 (SystemWatchdog)DeviceConfigurationssect ion).3 (withSIR,MIR,FIR, CIR supportandUARTRTS/CTSflow control)(UART0 SupportsModemInterface)SPI4 (Eachsupportingup to 4 slavedevices)8 DeviceOverviewCopyright 2013,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLinks:D M385DM388DM385, MARCH2013 REVISEDDECEMBER2013 Table2-2. Characteristicsof the Processor (continued)HARDWAREFEATURESDM38 5/DM3881 (1-bitor 4-bitor 8-bitmodes)andMMC/SD/SDIO1 (8-bitmode)or2 (1-bitor 4-bitmodes)I2C4 Masteror SlaveMediaControllerControlsHDVPSS,HDVIC P2, and ISS2 (6/2 Serializers,eachwithMcASPT ransmit/Receiveand DIT capability)RTC1 GPIOUp to 125 pinsSpinlockModule1 (up to 128 H/WSemaphores)MailboxModule1 (with12 Mailboxes)Size(Bytes)640 KBRAM,48 KBROMARM32 KBI-cache32 KBD-cache256 KBL