TMS320C5505 Fixed-Point Digital Signal Processor (Rev. F)

1 AUGUST2010 REVISEDSEPTEMBER2013 TMS320C5505 fixed -PointDigitalSignalProcessorCheckfo r Samples:TMS320C55051 High-Performance,Low-Power,TMS320C55x UniversalAsynchronousReceiver/Transmitte rFixed-PointDigitalSignalProcessor(UART) , ,10-, , Serial-PortInterface(SPI)WithFourChip-Cy cleTimeSelects 60-, 75-, 100-,120-, 150-MHzClockRate Master/SlaveInter-IntegratedCircuit(I2C Bus ) One/TwoInstructionsExecutedper Cycle FourInter-ICSound(I2S Bus ) for DataTransport DualMultipliers[Up to 200, 240,or 300 MillionMultiply-Accumulatesper Second High-(MMACS)]SpeedPHYthat Supports: TwoArithmetic/LogicUnits(ALUs) Full-and High-SpeedDevice ThreeInternalData/OperandReadBuses LCDB ridgeWithAsynchronousInterfaceand TwoInternalData/OperandWriteBuses Tightly-CoupledFFT HardwareAccelerator Software-CompatibleWithC55xDevices 10-Bit4-InputSuccessiveApproximation(SAR ) IndustrialTemperatureDevicesAvailableADC 320 KBytesZero-WaitStateOn-ChipRAM, Real-TimeClock(RTC)WithCrystalInput,With Composedof:SeparateClockDomainand PowerSupply 64K Bytesof Dual-AccessRAM(DARAM), FourCoreIsolatedPowerSupplyDomains:8 Blocksof 4K x 16-BitAnalog,RTC,CPUand Peripherals,and USB 256 KBytesof Single-AccessRAM(SARAM), FourI/O IsolatedPowerSupplyDomains.

2 RTC32 Blocksof 4K x 16-BitI/O, EMIFI/O, USBPHY,and DVDDIO 128 KBytesof ZeroWait-StateOn-ChipROM OneintegratedLDO(ANA_LDO)to powerDSP(4 Blocksof 16K x 16-Bit)PLL (VDDA_PLL) and 10-bitSARADC(VDDA_ANA) 4M x 16-BitMaximumAddressableExternal Low-PowerS/W ProgrammablePhase-LockedMemorySpace(SDRA M/mSDRAM)Loop(PLL)ClockGenerator 16-/8-BitExternalMemoryInterface(EMIF)wi th On-ChipROMB ootloader(RBL)to BootFromGluelessInterfaceto:NANDF lash,NORF lash,SPI EEPROM,SPIS erialFlashor I2C EEPROM 8-/16-BitNANDF lash,1- and 4-BitECC (JTAG) 8-/16-BitNORF lashBoundary-Scan-Compatible AsynchronousStaticRAM(SRAM) Up to 26 General-PurposeI/O (GPIO)Pins 16-bitSDRAM/mSDRAM( , , ,and(MultiplexedWithOtherDeviceFunctions ) ) 196-TerminalPb-FreePlasticBGA(BallGrid DirectMemoryAccess(DMA)ControllerArray)( ZCHS uffix) FourDMAWith4 ChannelsEach(16- (60 or 75 MHz), , , ,ChannelsTotal)or Three32-BitGeneral-PurposeTimers (100,120 MHz), , , , OneSelectableas a Watchdogand/orGPor TwoMultiMediaCard/SecureDigital(MMC/SD) (150 MHz)

3 , , , I/Os1 Pleasebe awarethat an importantnoticeconcerningavailability,st andardwarranty,and use in criticalapplicationsofTexasInstrumentsse miconductorproductsand disclaimerstheretoappearsat the end of this trademarksare the propertyof currentas of 2010 2013,TexasInstrumentsIncorporatedspecifi cationsper the termsof the necessarilyincludetestingof all AUGUST2010 WirelessAudioDevices(Headsets,Microphone s,Speakerphones) EchoCancellationHeadphones PortableMedicalDevices VoiceApplications IndustrialControls FingerprintBiometrics deviceis a memberof TI's TMS320C5000 fixed -pointDigitalSignalProcessor(DSP)pr oductfamilyand is designedfor fixed -pointDSPis basedon the TMS320C55x C55x DSParchitectureachieveshigh performanceand low powerthroughincreasedparallelismand total focuson CPUsupportsan internalbus structurethat is composedof one programbus, one32-bitdatareadbus and two 16-bitdatareadbuses,two 16-bitdatawritebuses,and additionalbusesdedicatedto peripheraland abilityto performup to four 16-bitdatareadsand two 16-bitdatawritesin a devicealsoincludesfour DMAcontrollers,eachwith 4 channels,providingdatamovementfor performone 32-bitdatatransferper cycle,in paralleland independentof (MAC)units,eachcapableof 17-bitx 17-bitmultiplicationand a 32-bitadd in a central40-bitarithmetic/logicunit (ALU)

4 Is supportedbyan of the ALUsis underinstructionset control,providingthe abilityto optimizeparallelactivityand managedin the AddressUnit (AU)and DataUnit (DU)of the C55xCPUsupportsa variablebytewidthinstructionset for InstructionUnit (IU) performs32-bitprogramfetchesfrominternal or externalmemoryand queuesinstructionsfor theProgramUnit (PU).The ProgramUnit decodesthe instructions,directstasksto the AddressUnit (AU)andDataUnit (DU)resources,and managesthe fully executionof general-purposeinputand outputfunctionsalongwith the 10-bitSARADC providesufficientpins forstatus,interrupts,and bit I/O for LCDdisplays,keyboards,and supportedthroughtwo MultiMediaCard/SecureDigital(MMC/SD)peri pherals,fourInter-ICSound(I2 SBus )modules,oneSerial-PortInterface(SPI)wit hup to 4 chipselects,oneI2C multi-masterandslaveinterface,and a UniversalAsynchronousReceiver/Transmitte r(UART) deviceperipheralset includesan externalmemoryinterface(EMIF)that providesgluelessaccesstoasynchronousmemo rieslike EPROM,NOR,NAND,and SRAM,as well as to high-speed,high-densitymemoriessuchas synchronousDRAM(SDRAM)and mobileSDRAM(mSDRAM).

5 Additionalperipheralsinclude:a high-speedUniversalSerialBus ( )devicemodeonly,and a real-timeclock(RTC).Thisdevicealsoinclud esthreegeneral-purposetimerswithone configurableas a watchdogtimer,and ananalogphase-lockedloop (APLL) addition,the deviceincludesa to 1024-point(in powerof 2) real and (ANA_LDO)to V to the DSPPLL(VDDA_PLL) and 10-bitSARADC(VDDA_ANA).Note:ANA_LDOcan only providea V. WhentheDSPPLL V (PLLOUT> 120 MHz),an externalsupplyis requiredto V to the DSPPLL (VDDA_PLL).2 fixed -PointDigitalSignalProcessorCopyrig ht 2010 2013, AUGUST2010 REVISEDSEPTEMBER2013 Thedeviceis supportedby the industry s award-winningeXpressDSP , CodeComposerStudio IntegratedDevelopmentEnvironment(IDE),DS P/BIOS , TexasInstruments algorithmstandard,and theindustry s featurescodegenerationtoolsincludinga C Compilerand Linker,RTDX , XDS100 , XDS510 , XDS560 emulationdevicedrivers, deviceis also supportedby the C55xDSPL ibrarywhichfeaturesmorethan50foundationa lsoftwarekernels(FIRfilters,IIR filters,FFTs,and variousmathfunctions)as well as 2010 2013,TexasInstrumentsIncorporatedFixed-P ointDigitalSignalProcessor3 SubmitDocumentationFeedbackProductFolder Links.

6 TMS320C5505 PLL/ClockGeneratorPowerManagementPinMult iplexingJTAG Interface64 KB DARAM256 KB SARAM128 KB ROMS witched Central Resource (SCR)InputClock(s)FFT HardwareAcceleratorC55x DSP CPUDSP SystemLCDB ridgeDisplayI S(x4)2I C2 SPIUARTS erial Interfaces10-BitSARADCApp-SpecUSB (HS)[DEVICE]ConnectivityPeripheralsDMA(x 4)InterconnectNAND, NOR,SRAM,SDRAM/mSDRAMP rogram/Data StorageMMC/SD(x2)SystemGP Timer(x2)RTCGP Timeror WDLDOTMS320C5505 SPRS660F AUGUST2010 showsthe functionalblockdiagramof the FunctionalBlockDiagram4 fixed -PointDigitalSignalProcessorCopyrig ht 2010 2013, AUGUST2010 ControlSignalTransition1 ,CLKIN, (DMA) (EMIF).. (MMC/SD).. (RTC).. (I2C)..1103 (UART).. (I2S).. (LCDC).. Interface(SPI).. (USB) Deviceand (UnlessOtherwiseNoted).

7 MechanicalPackagingand OrderableRangesof SupplyVoltageand (UnlessOtherwiseNoted).. PeripheralInformationand 2010 2013,TexasInstrumentsIncorporatedContent s5 SubmitDocumentationFeedbackProductFolder Links: TMS320C5505 TMS320C5505 SPRS660F AUGUST2010 :Pagenumbersfor previousrevisionsmay differfrompagenumbersin the technicalchangesmadeto the :Applicableupdatesto the TMS320C5000devicefamily,specificallyrela tingto the device( ) whichis now in the productiondata(PD)stageof developmenthavebeenincorporated. 150 MHzis now supportedSEEADDITIONS/MODIFICATIONS/DELE TIONSG lobal Addednotesto clarifythat CVDDRTC mustalwaysbe poweredby an externalpowersupplyandnoneof the on-chipLDOscan ,Characteristicsof the C5505 Processor :DeviceOverview DeletedPowerCharacterization Updatedaddressesfor MMC/SD0and MMC/SD1in Table2-4, ,RESET,Interrupts,and JTAGT erminalFunctions:TerminalFunctions Deletedduplicatenoteon ,ExternalMemoryInterface(EMIF)TerminalFu nctions: Changednotefor 16-bitasynchronousmemoryto connectEM_A[20:0]to memoryaddresspins[21:1].

8 Table2-13, Addedpower-oninformationfor USB_VBUS,USB_VDDA3P3, USB_VDDA1P3, and ,Reservedand No ConnectsTerminalFunctions: UpdatedRSV16descriptionto tie directlyto AddednotestatingDeviceID registersare ,BootSequence: Addedstepsto set registerconfigurationand copybootimagesections(steps15 and 16). ChangedFigure3-1,BootloaderSoftwareArchi tecture. Addedresetdefaultto pin UpdatedDeviceOperatingLife Power-OnHours(POH)to 80,000and 34, Addednotefor core(CVDD) supplypower(P). UpdatedESDS tressVoltagevaluefor HBMto > , ,PLL ClockFrequencyRanges:PLL Device-Specific Updatedmaximumvaluefor 2010 2013, AUGUST2010 REVISEDSEPTEMBER2013 SEEADDITIONS/ ,TimingRequirementsfor Wake-UpFromIDLE:Wake-UpFromIDLE Changedminimumvalueto s from10 ,SwitchingCharacteristicsOverRecommended OperatingConditionsFor Wake-UpFromIDLE: Changedparameterdescriptionto, "Delaytime,WAKEUP pulsecompleteto CPUactive.

9 " Moved2 to WAKEUP pulsecompletefromwake-upeventhigh in Figure5-13, :ExternalMemory Updateddevicelimitationson EM_SDCLK whenDVDDEMIF= V and (EMIF) Addednotesto timingand Addedto wake-upsequencein , (RTC) Updatedresetvaluefor WU_DOUT from0 to Section7 and 2010 2013,TexasInstrumentsIncorporatedContent s7 SubmitDocumentationFeedbackProductFolder Links: TMS320C5505 TMS320C5505 SPRS660F AUGUST2010 , providesan overviewof the tablesshowsignificantfeaturesof thedevice,includingthe capacityof on-chipRAM,the peripherals,the CPUfrequency,and the packagetypewithpin moredetailedinformationon the actualdevicepart numberand maximumdeviceoperatingfrequency,see ,Deviceand Characteristicsof the C5505 ProcessorHARDWAREFEATURESC5505 PeripheralsAsynchronous(8/16-bitbus width)SRAM,ExternalMemoryInterface(EMIF) Flash(NOR,NAND),Not all peripheralpins areSDRAMand MobileSDRAM(16-bitbus width)(1)availableat the sametime(for moredetail,see theFourDMAcontrollerseachwith four channels,DMAD eviceConfigurationfor a total of 16 channelssection).

10 2 32-BitGeneral-Purpose(GP)TimersTimers1 AdditionalTimerConfigurableas a 32-BitGP Timerand/oraWatchdogUART1 (withRTS/CTSflow control)SPI1 with 4 chip selectsI2C1 (Master/Slave)I2S4 (TwoChannel,Full DuplexCommunication) (Deviceonly)High-and Full-SpeedDevice2 MMC/SD,256 byte read/writebuffer,max 50-MHzclockforMMC/SDSD cards,and signalingfor DMAtransfersLCDB ridge1 (8-bitor 16-bitasynchronousparallelbus)ADC(Succes siveApproximation[SAR])1 (10-bit,4-input,16- s conversiontime)Real-TimeClock(RTC)1 (CrystalInput,SeparateClockDomainand PowerSupply)FFT HardwareAccelerator1 (Supports8 to 1024-point16-bitreal and complexFFT)Up to 26 pins (with1 AdditionalGeneral-PurposeOutput(XF)Gener al-PurposeInput/OutputPort (GPIO)and 4 Special-PurposeOutputsfor Use WithSAR)Size(Bytes)320 KBRAM,128 KBROM 64 KBOn-ChipDual-AccessRAM(DARAM)On-ChipMem oryOrganization 256 KBOn-ChipSingle-AccessRAM(SARAM) 128 KBOn-ChipSingle-AccessROM(SAROM)JTAGIDR egisterJTAGBSDL_IDsee Figure5-44(Valueis: 0x1B8FE02F) or 75 or 120 , , (60, 75 MHz)Core(V) V (100,120 MHz) V (150 MHz)I/O (V) V, V, , V, 4 mA max currentfor PLL (VDDA_PLL), SAR,and powerLDOANA_LDOmanagementcircuits(VDDA_A NA)PLL OptionsSoftwareProgrammableMultiplierx4 to x4099multiplierBGAP ackage10 x 10 mm196-PinBGA(ZCH)(1)For moreinformationon SDRAM devicessupport,see ,ExternalMemoryInterface(EMIF).