DRV8301 Three-Phase Gate Driver With Dual …

1 Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design DRV8301 . SLOS719F AUGUST 2011 REVISED JANUARY 2016. DRV8301 Three-Phase gate Driver With Dual Current Shunt Amplifiers and Buck Regulator 1 Features 3 Description . 1 6-V to 60-V Operating Supply Voltage Range The DRV8301 is a gate Driver IC for Three-Phase motor drive applications. The device provides three Source and Sink gate Drive Current half-bridge drivers, each capable of driving two N- Capability channel MOSFETs. The DRV8301 supports up to Slew Rate Control for EMI Reduction source and peak current capability. The Bootstrap gate Driver With 100% Duty Cycle DRV8301 can operate off of a single power supply Support with a wide range from 6-V to 60-V.

2 The device uses a bootstrap gate Driver architecture with trickle charge 6- or 3-PWM Input Modes circuitry to support 100% duty cycle. The DRV8301 . Dual Integrated Current Shunt Amplifiers With uses automatic handshaking when the high-side or Adjustable Gain and Offset low-side MOSFET is switching to prevent flow of Integrated Buck Converter current. Integrated VDS sensing of the high-side and low-side MOSFETs is used to protect the external and 5-V Interface Support power stage against overcurrent conditions. SPI. The DRV8301 includes two current shunt amplifiers Protection Features: for accurate current measurement. The amplifiers Programmable Dead Time Control (DTC) support bidirectional current sensing and provide an Programmable Overcurrent Protection (OCP) adjustable output offset up to 3 V.

3 PVDD and GVDD Undervoltage Lockout The DRV8301 also includes an integrated switching (UVLO) mode buck converter with adjustable output and GVDD Overvoltage Lockout (OVLO) switching frequency. The buck converter can provide up to A to support MCU or additional system Overtemperature Warning/Shutdown power needs. (OTW/OTS). The SPI provides detailed fault reporting and flexible Reported Through nFAULT, nOCTW, and SPI parameter settings such as gain options for the Registers current shunt amplifiers and slew rate control of the gate drivers. 2 Applications 3-Phase BLDC and PMSM Motors Device Information(1). PART NUMBER PACKAGE BODY SIZE (NOM). CPAPs and Pumps DRV8301 HTSSOP (56) mm mm E-bikes (1) For all available packages, see the orderable addendum at Power Tools the end of the data sheet.

4 Robotics and RC Toys Industrial Automation Simplified Schematic 6 to 60 V. PWM DRV8301 . SPI gate Drive 3-Phase N-Channel MOSFETs Diff Amps Brushless MCU. Pre- Driver M. nFAULT Sense Buck nOCTW Converter Vcc (Buck). 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8301 . SLOS719F AUGUST 2011 REVISED JANUARY 2016 Table of Contents 1 Features .. 1 Feature 15. 2 Applications .. 1 Device Functional Modes .. 20. 3 Description .. 1 21. Register Maps .. 22. 4 Revision 2. 5 Pin Configuration and Functions .. 3 8 Application and Implementation .. 24. Application 24.

5 6 6. Typical Application .. 25. Absolute Maximum Ratings .. 6. ESD 6 9 Power Supply 28. Bulk Capacitance .. 28. Recommended Operating 7. Thermal Information .. 7 10 29. Electrical 8 Layout Guidelines .. 29. Current Shunt Amplifier 9 Layout Example .. 30. Buck Converter Characteristics .. 10 11 Device and Documentation Support .. 31. SPI Timing Requirements (Slave Mode Only) .. 10 Documentation Support .. 31. gate Timing and Protection Switching Community 31. Characteristics .. 11 Trademarks .. 31. Typical Characteristics .. 12 Electrostatic Discharge Caution .. 31. 7 Detailed Description .. 13 Glossary .. 31. Overview .. 13 12 Mechanical, Packaging, and Orderable Functional Block Diagram .. 14 Information.

6 31. 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2015) to Revision F Page Changed VEN_BUCK in Buck Converter Characteristics From: MIN = V and MAX = V To: MIN = V and MAX = V.. 10. Changes from Revision D (August 2015) to Revision E Page Corrected table note for dead time programming definition .. 11. Updated description of gate Driver power-up sequencing errata .. 24. Fixed connections for pin 25 in Figure 7 .. 25. Changes from Revision C (January 2015) to Revision D Page VPVDD absolute max voltage rating reduced from 70 V to 65 V .. 6. Clarification made on how the OCP status bits report in Overcurrent Protection and Reporting (OCP).

7 17. Update to PVDD1 undervoltage protection in Undervoltage Protection (PVDD_UV and GVDD_UV) describing specific transient brownout issue.. 18. Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse lengths.. 20. Added gate Driver power-up sequencing errata .. 24. Added Community Resources .. 31. Changes from Revision B (August 2013) to Revision C Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .. 6. 2 Submit Documentation Feedback Copyright 2011 2016, Texas Instruments Incorporated Product Folder Links: DRV8301 .

8 DRV8301 . SLOS719F AUGUST 2011 REVISED JANUARY 2016. 5 Pin Configuration and Functions DCA Package 56-Pin HTSSOP with PowerPAD . Top View RT_CLK 1 56 SS_TR. COMP 2 55 EN_BUCK. VSENSE 3 54 PVDD2. PWRGD 4 53 PVDD2. nOCTW 5 52 BST_BK. nFAULT 6 51 PH. DTC 7 50 PH. nSCS 8 49 VDD_SPI. SDI 9 48 BST_A. SDO 10 47 GH_A. SCLK 11 46 SH_A. GND (57) - PWR_PAD. DC_CAL 12 45 GL_A. GVDD 13 44 SL_A. CP1 14 43 BST_B. CP2 15 42 GH_B. EN_GATE 16 41 SH_B. INH_A 17 40 GL_B. INL_A 18 39 SL_B. INH_B 19 38 BST_C. INL_B 20 37 GH_C. INH_C 21 36 SH_C. INL_C 22 35 GL_C. DVDD 23 34 SL_C. REF 24 33 SN1. SO1 25 32 SP1. SO2 26 31 SN2. AVDD 27 30 SP2. AGND 28 29 PVDD1. Pin Functions PIN. TYPE (1) DESCRIPTION. NAME NO. Resistor timing and external clock for buck regulator.

9 Resistor should connect to GND (PowerPAD ). RT_CLK 1 I. with very short trace to reduce the potential clock jitter due to noise. COMP 2 O Buck error amplifier output and input to the output switch current comparator. VSENSE 3 I Buck output voltage sense pin. Inverting node of error amplifier. An open-drain output with external pullup resistor required. Asserts low if buck output voltage is low PWRGD 4 O. due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down Overcurrent and/or overtemperature warning indicator. This output is open drain with external pullup nOCTW 5 O. resistor required. Programmable output mode via SPI registers. nFAULT 6 O Fault report indicator. This output is open drain with external pullup resistor required.

10 DTC 7 I Dead-time adjustment with external resistor to GND. nSCS 8 I SPI chip select SDI 9 I SPI input SDO 10 O SPI output (1) KEY: I =Input, O = Output, P = Power Copyright 2011 2016, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: DRV8301 . DRV8301 . SLOS719F AUGUST 2011 REVISED JANUARY 2016 Pin Functions (continued). PIN. TYPE (1) DESCRIPTION. NAME NO. SCLK 11 I SPI clock signal When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset DC_CAL 12 I. calibration can be done through external microcontroller. GVDD 13 P Internal gate Driver voltage regulator. GVDD cap should connect to GND. CP1 14 P Charge pump pin 1, ceramic capacitor should be used between CP1 and CP2.