DS90C383,DS90CF384 - TI.com

1 ds90c383 ,DS90CF384DS90C383/ ds90cf384 + Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, + LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzLiterature Number: SNLS124DS90C383/ ds90cf384 + Programmable LVDS Transmitter 24-Bit Flat PanelDisplay (FPD) Link 65 MHz, + LVDS Receiver24-Bit Flat Panel Display (FPD) Link 65 MHzGeneral DescriptionThe ds90c383 transmitter converts 28 bits of CMOS/TTLdata into four LVDS (Low Voltage Differential Signaling) datastreams. A phase-locked transmit clock is transmitted in par-allel with the data streams over a fifth LVDS link.

2 Every cycleof the transmit clock 28 bits of input data are sampled andtransmitted. The ds90cf384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a trans-mit clock frequency of 65 MHz, 24 bits of RGB data and 3bits of LCD timing and control data (FPLINE, FPFRAME,DRDY) are transmitted at a rate of 455 Mbps per LVDS datachannel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmableedge data strobes for convenient interface with a variety ofgraphics controllers.

3 The transmitter can be programmed forRising edge strobe or Falling edge strobe through a dedi-cated pin. A Rising edge transmitter will inter-operate with aFalling edge receiver ( ds90cf384 ) without any translationlogic. The ds90cf384 is also offered in 64 ball, finepitch ball grid array(FBGA) package which provides a 44%reduction in PCB footprint (available Q3, 1999).This chipset is an ideal means to solve EMI and cable sizeproblems associated with wide, high speed TTL to 65 MHz shift clock supportnProgrammable transmitter ( ds90c383 ) strobe select(Rising or Falling edge strobe)nSingle supplynChipset (Tx + Rx) power consumption<250 mW (typ)nPower-down mode (< mW total)nSingle pixel per clock XGA (1024x768)

4 ReadynSupports VGA, SVGA, XGA and higher to 227 Megabytes/sec bandwidthnUp to Gbps throughputnNarrow bus reduces cable size and costn290 mV swing LVDS devices for low EMInPLL requires no external componentsnLow profile 56-lead TSSOP also available in 64 ball, fine pitchball grid array(FBGA) packagenFalling edge data strobe ReceivernCompatible with TIA/EIA-644 LVDS standardnESD rating>7kVnOperating Temperature: 40 C to +85 CBlock DiagramsTRI-STATE is a registered trademark of National Semiconductor 1999DS90C383/ ds90cf384 + Programmable LVDS 24-Bit-Color Flat Panel Display (FPD)Link 65 MHz 1999 National Semiconductor Diagrams(Continued)DS90C383DS012887-1 Order Number ds90c383 MTDSee NS Package Number MTD56DS90CF384DS012887-24 Order Number ds90cf384 MTD or ds90cf384 SLCSee NS Package Number MTD56 or Maximum Ratings(Note 1)

5 If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and Voltage (VCC) to +4 VCMOS/TTL Input Voltage to (VCC+ )CMOS/TTL Output Voltage to (VCC+ )LVDS Receiver Input Voltage to (VCC+ )LVDS Driver Output Voltage to (VCC+ )LVDS Output Short CircuitDurationContinuousJunction Temperature+150 CStorage Temperature 65 C to +150 CLead Temperature(Soldering, 4 sec for TSSOP)+260 CSolder Reflow Temperature(20 sec for FBGA)+220 CMaximum Package Power Dissipation Capacity 25 CMTD56 (TSSOP) WPackage mW/ C above +25 mW/ C above +25 CMaximum Package Power Dissipation Capacity 25 CSLC64A WPackage mW/ C above +25 CESD Rating(HBM, k , 100 pF)>7kVRecommended OperatingConditionsMinNomMaxUnitsSupply Voltage (VCC) Free AirTemperature (TA) 40+25+85 CReceiver Input Noise Voltage (VCC)

6 100mVPPE lectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise DC SPECIFICATIONSVIHHigh Level Input Level Input Level Output VoltageIOH= Level Output VoltageIOL= 2 Clamp VoltageICL= 18 mA CurrentVIN=VCC, GND, or 10 AIOSO utput Short Circuit CurrentVOUT= 0V 60 120mALVDS DC SPECIFICATIONSVODD ifferential Output VoltageRL= 100 250345450mV VODC hange in VODbetween35mVcomplimentary output statesVOSO ffset Voltage (Note 4) VOSC hange in VOSbetween35mVcomplimentary output statesIOSO utput Short Circuit CurrentVOUT= 0V, RL= 100 5mAIOZO utput TRI-STATE CurrentPower Down = 0V, 1 10 AVOUT=0 VorVCCVTHD ifferential Input High ThresholdVCM= + +100mVVTLD ifferential Input Low Threshold 100mVIINI nput CurrentVIN= + , VCC= 10 AVIN= 0V, VCC= 10 ATRANSMITTER SUPPLY CURRENTICCTWT ransmitter Supply CurrentRL= 100 ,CL= 5 pF,f = MHz3145mAWorst CaseWorst Case Patternf = MHz3250mA(Figures 1, 3),TA= 40 C to +85 Cf = 65 Characteristics(Continued)

7 Over recommended operating supply and temperature ranges unless otherwise SUPPLY CURRENTICCTGT ransmitter Supply CurrentRL= 100 ,CL= 5 pF,f = MHz2335mA16 Grayscale16 Grayscale Patternf = MHz2840mA(Figures 2, 3 ),TA= 40 C to +85 Cf = 65 MHz3145mAICCTZT ransmitter Supply CurrentPower Down = Low1055 APower DownDriver Outputs in TRI-STATE underPower Down ModeRECEIVER SUPPLY CURRENTICCRW Receiver Supply CurrentCL= 8 pF,f = MHz4965mAWorst CaseWorst Case Patternf = MHz5370mA(Figures 1, 4 ),TA= 40 C to +85 Cf = 65 MHz78105mAICCRGR eceiver Supply Current,CL= 8 pF,f = MHz2845mA16 Grayscale16 Grayscale Patternf = MHz3047mA(Figures 2, 4 ),TA= 40 C to +85 Cf = 65 MHz4360mAICCRZR eceiver Supply CurrentPower Down = Low1055 APower DownReceiver Outputs Stay Low duringPower Down ModeNote 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed.

8 They are not meant to imply that the deviceshould be operated at these limits. The tables of Electrical Characteristics specify conditions for device 2:Typical values are given for VCC= and TA= + 3:Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwisespeci-fied (except VODand VOD).Note 4:VOSpreviously referred as Switching CharacteristicsOver recommended operating supply and 40 C to +85 C ranges unless otherwise specifiedSymbolParameterMinTypMaxUnitsLL HTLVDS Low-to-High Transition Time(Figure 3 ) High-to-Low Transition Time(Figure 3 ) IN Transition Time(Figure 5 )5nsTCCSTxOUT Channel-to-Channel Skew(Figure 6 )250psTPPos0 Transmitter Output Pulse Position for Bit 0(Figure 17 )

9 F = 65 MHz Output Pulse Position for Bit Output Pulse Position for Bit Output Pulse Position for Bit Output Pulse Position for Bit Output Pulse Position for Bit Output Pulse Position for Bit IN Period(Figure 7)15T50nsTCIHTxCLK IN High Time(Figure 7) IN Low Time(Figure 7) Setup to TxCLK IN(Figure 7 )f = 65 Hold to TxCLK IN(Figure 7 )0nsTCCDTxCLK IN to TxCLK OUT Delay 25 C, VCC= (Figure 9 ) Phase Lock Loop Set(Figure 11 )10msTPDDT ransmitter Power Down Delay(Figure 15 ) Switching CharacteristicsOver recommended operating supply and 40 C to +85 C ranges unless otherwise specifiedSymbolParameterMinTypMaxUnitsCL HTCMOS/TTL Low-to-High Transition Time(Figure 4 ) High-to-Low Transition Time(Figure 4 ) Input Strobe Position for Bit 0(Figure 18 )f = 65 Input Strobe Position for Bit Input Strobe Position for Bit Input Strobe Position for Bit Input Strobe Position for Bit Input Strobe Position for Bit Input Strobe Position for Bit Skew Margin (Note 5)(Figure 19 )

10 F = 65 MHz400psRCOPRxCLK OUT Period(Figure 8)15T50nsRCOHRxCLK OUT High Time(Figure 8 )f = 65 OUT Low Time(Figure 8) Setup to RxCLK OUT(Figure 8 ) Hold to RxCLK OUT(Figure 8 ) IN to RxCLK OUT Delay 25 C, VCC= (Figure 10 ) Phase Lock Loop Set(Figure 12 )10msRPDDR eceiver Power Down Delay(Figure 16 )1 sNote 5:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (minand max) and the receiver input setup and hold time (internal data sampling window-RSPOS).