DS90UB947-Q1 1080p OpenLDI to FPD-Link III …

1 Product Sample & Technical Tools & Support &. Folder Buy Documents Software Community DS90UB947-Q1 . SNLS454 NOVEMBER 2014. DS90UB947-Q1 1080p OpenLDI to FPD-Link III Serializer 1 Features 3 Description 1 Supports Clock Frequency up to 170 MHz for The DS90UB947-Q1 is an OpenLDI to FPD-Link III. WUXGA (1920x1200) and 1080p60 Resolutions bridge device which, in conjunction with the FPD-Link III DS90UB940-Q1/DS90UB948-Q1 deserializers, with 24-Bit Color Depth provides 1-lane or 2-lane high-speed serial streams Single and Dual FPD-Link III Outputs over cost-effective 50 single-ended coaxial or 100.

2 Single Link: Up to 96 MHz Pixel Clock differential shielded twisted-pair (STP) cables. It Dual Link: Up to 170 MHz Pixel Clock serializes an OpenLDI input supporting video resolutions up to WUXGA and 1080p60 with 24-bit Single and Dual OpenLDI (LVDS) Receiver color depth. Configurable 18-Bit RGB or 24-Bit RGB. The FPD-Link III interface supports video and audio High Speed Back Channel Supporting GPIO up to data transmission and full duplex control, including 2 Mbps I2C and SPI communication, over the same Supports up to 15 Meters of Cable with Automatic differential link. Consolidation of video data and Temperature and Aging Compensation control over two differential pairs reduces the interconnect size and weight and simplifies system I2C (Master/Slave) with 1 Mbps Fast-Mode Plus design.

3 EMI is minimized by the use of low voltage SPI Pass-Through Interface differential signaling, data scrambling, and Backward compatible with DS90UB926Q-Q1 and randomization. In backward compatible mode, the DS90UB928Q-Q1 FPD-Link III Deserializers device supports up to WXGA and 720p resolutions Automotive Grade Product: AEC-Q100 Grade 2 with 24-bit color depth over a single differential link. Qualified The DS90UB947-Q1 supports multi-channel audio received through an external I2S interface. Audio 2 Applications data received by the device is encrypted and sent over the FPD-Link III interface where it is regenerated Automotive Infotainment: by the deserializer.

4 IVI Head Units and HMI Modules Rear Seat Entertainment Systems Device Information(1). PART NUMBER PACKAGE BODY SIZE (NOM). Digital Instrument Clusters DS90UB947-Q1 VQFN RGC (64) mm X mm Security and Surveillance Camera (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Applications Diagram VDDIO VDDIO. or FPD-Link FPD-Link FPD-Link III ( OpenLDI ). ( OpenLDI ) 2 lanes @3 Gbps / per Lane CLK+/- CLK+/- DOUT0+ RIN0+ D0+/- D0+/- DOUT0- RIN0- D1+/- D1+/- DOUT1+ RIN1+ D2+/- LVDS. D2+/- Display Graphics DOUT1- RIN1- D3+/- 1080p60. Processor D3+/- DS90UB947-Q1 DS90UB948-Q1 or Graphic Serializer Deserializer CLK2+/- Processor D4+/- D4+/- D5+/- D5+/- D6+/- I2C I2C.

5 IDx IDx D6+/- D7+/- D_GPIO D_GPIO. (SPI) (SPI) D7+/- 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UB947-Q1 . SNLS454 NOVEMBER 2014 Table of Contents 1 Features .. 1 Feature 14. 2 Applications .. 1 Device Functional 31. 3 Description .. 1 33. Register Maps .. 37. 4 Applications Diagram .. 1. 5 Revision 2 9 Application and Implementation .. 65. Applications 65. 6 Pin Configuration and Functions .. 3. Typical Applications .. 65.

6 7 6. 10 Power Supply Recommendations .. 70. Absolute Maximum Ratings .. 6. Power Up Requirements And PDB 70. Handling 6. Recommended Operating 6 11 71. Layout Guidelines .. 71. Thermal Information .. 6. Layout Example .. 72. DC Electrical Characteristics .. 7. AC Electrical 8 12 Device and Documentation Support .. 73. DC And AC Serial Control Bus Characteristics .. 9 Documentation Support .. 73. Recommended Timing for the Serial Control Bus .. 10 Trademarks .. 73. Typical Characteristics .. 13 Electrostatic Discharge Caution .. 73. Glossary .. 73. 8 Detailed Description .. 14. Overview .. 14 13 Mechanical, Packaging and Orderable Functional Block Diagram.

7 14. Information .. 73. 5 Revision History DATE REVISION NOTES. November 2014 * Initial release. 2 Submit Documentation Feedback Copyright 2014, Texas Instruments Incorporated Product Folder Links: DS90UB947-Q1 . DS90UB947-Q1 . SNLS454 NOVEMBER 2014. 6 Pin Configuration and Functions 64 PINS. Top View I2S_CLK / GPIO8_REG. I2S_WC / GPIO7_REG. I2S_DB / GPIO5_REG. I2S_DA / GPIO6_REG. D_GPIO2 / SPLK. D_GPIO1 / MISO. D_GPIO0 / MOSI. I2S_DD / GPIO3. I2S_DC / GPIO2. D_GPIO3 / SS. VDDL11. VDDIO. RES2. RES3. SDA. SCL. 48. 47. 46. 45. 44. 43. 42. 41. 40. 39. 38. 37. 36. 35. 34. 33. INTB 49 32 MODE_SEL1. VDDOA11 50 31 PDB.

8 D0- 51 30 RES1. D0+ 52 29 RES0. D1- 53 28 VDDHS11. D1+ 54 27 DOUT0+. D2- 55 26 DOUT0- D2+ 56 DS90UB947-Q1 25 VDDS11. CLK- 57 24 VDD18. Top view CLK+ 58 23 DOUT1+. D3- 59 22 DOUT1- D3+ 60 21 VDDHS11. VDDOP11 61 20 LF. VDD18 62 DAP = GND 19 IDx LFOLDI 63 18 MODE_SEL0. VDDOA11 64 17 VDDP11. 10. 11. 12. 13. 14. 15. 16. 1. 2. 3. 4. 5. 6. 7. 8. 9. VDDA11. I2 CSEL. GPIO0. GPIO1. VDDIO. VDDL11. D4- D4+. D5- D5+. D6- D6+. D7- D7+. REM_INTB. NC. Pin Functions Pin Name Pin # I/O, Type Description LVDS Input Pins D7- 7 I, LVDS Inverting LVDS Data Inputs D6- 5 Each pair requires external 100 differential termination for standard LVDS levels D5- 3.

9 D4- 1. D3- 59. D2- 55. D1- 53. D0- 51. D7+ 8 I, LVDS True LVDS Data Inputs D6+ 6 Each pair requires external 100 differential termination for standard LVDS levels D5+ 4. D4+ 2. D3+ 60. D2+ 56. D1+ 54. D0+ 52. CLK- 57 I, LVDS Inverting LVDS Clock Input Each pair requires external 100 differential termination for standard LVDS levels CLK+ 58 I, LVDS True LVDS Clock Input Each pair requires external 100 differential termination for standard LVDS levels Copyright 2014, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: DS90UB947-Q1 . DS90UB947-Q1 . SNLS454 NOVEMBER 2014 Pin Functions (continued).

10 Pin Name Pin # I/O, Type Description LFOLDI 63 Analog OpenLDI Loop Filter Connect to a 10nF capacitor to GND. FPD-Link III Serial Pins DOUT0- 26 I/O FPD-Link III Inverting Output 0. The output must be coupled with a 33nF capacitor DOUT0+ 27 I/O FPD-Link III True Output 0. The output must be coupled with a 33nF capacitor DOUT1- 22 I/O FPD-Link III Inverting Output 1. The output must be coupled with a 33nF capacitor DOUT1+ 23 I/O FPD-Link III True Output 1. The output must be coupled with a 33nF capacitor LF 20 Analog FPD-Link III Loop Filter Connect to a 10nF capacitor to GND. Control Pins SDA 48 IO, Open-Drain I2C Data Input / Output Interface Open drain.