F28M36x Concerto™ Microcontrollers - TI.com

1 Product Order Technical Tools & Support &. Folder Now Documents Software Community F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2. F28M36H33C2, F28M36H33B2. SPRS825E OCTOBER 2012 REVISED DECEMBER 2017. F28M36x Concerto Microcontrollers 1 Device Overview 1. Features Master Subsystem ARM Cortex -M3 Control Subsystem TMS320C28x 32-Bit CPU. 125 MHz 150 MHz Embedded Memory C28x Core Hardware Built-in Self-Test Up to 1MB of Flash (ECC) Embedded Memory Up to 128KB of RAM (ECC or Parity) Up to 512KB of Flash (ECC). Up to 64KB of Shared RAM Up to 36KB of RAM (ECC or Parity).

2 2KB of IPC Message RAM Up to 64KB of Shared RAM. Five Universal Asynchronous 2KB of IPC Message RAM. Receiver/Transmitters (UARTs) IEEE-754 Single-Precision Floating-Point Unit Four Synchronous Serial Interfaces (SSIs) (FPU). and a Serial Peripheral Interface (SPI) Viterbi, Complex Math, CRC Unit (VCU). Two Inter-integrated Circuits (I2Cs) Serial Communications Interface (SCI). Universal Serial Bus On-the-Go (USB-OTG) + SPI. PHY I2C. 10/100 ENET 1588 MII 6-Channel Direct Memory Access (DMA). Two Controller Area Network, D_CAN, Modules 12 Enhanced Pulse Width Modulator (ePWM).

3 (Pin-Bootable) Modules 32-Channel Micro Direct Memory Access 24 Outputs (16 High-Resolution). ( DMA). Six 32-Bit Enhanced Capture (eCAP) Modules Dual Security Zones (128-Bit Password per Three 32-Bit Enhanced Quadrature Encoder Zone). Pulse (eQEP) Modules External Peripheral Interface (EPI). Multichannel Buffered Serial Port (McBSP). Micro Cyclic Redundancy Check ( CRC). EPI. Module One Security Zone (128-Bit Password). Four General-Purpose Timers Three 32-Bit Timers Two Watchdog Timer Modules Endianness: Little Endian Endianness: Little Endian Analog Subsystem Clocking Dual 12-Bit Analog-to-Digital Converters (ADCs).

4 On-chip Crystal Oscillator and External Clock Input Up to MSPS. Dynamic Phase-Locked Loop (PLL) Ratio Up to 24 Channels Changes Supported Four Sample-and-Hold (S/H) Circuits Digital, Analog, I/O Design Up to Six Comparators With 10-Bit Digital-to- Interprocessor Communications (IPC) Analog Converter (DAC). 32 Handshaking Channels Package Four Channels Generate IPC Interrupts 289-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA). Can be Used to Coordinate Transfer of Data Through IPC Message RAMs Temperature Options: Up to 142 Individually Programmable, Multiplexed T: 40 C to 105 C Junction General-Purpose Input/Output (GPIO) Pins S: 40 C to 125 C Junction Glitch-free I/Os 1.

5 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2. F28M36H33C2, F28M36H33B2. SPRS825E OCTOBER 2012 REVISED DECEMBER 2017 Applications Servo Drives Electric Vehicle/Hybrid Electric Vehicle (EV/HEV). High-End AC Inverters Chargers Industrial UPS Power Line Communications Solar Inverters Description The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems.

6 The F28M36x family of devices is the second series in the Concerto family. The communications subsystem is based on the industry-standard 32-bit ARM Cortex-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C, and an external interface. The real-time control subsystem is based on TI's industry-leading proprietary 32-bit C28x floating-point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures all as implemented by TI's TMS320C2000 Piccolo and Delfino families.

7 In addition, the C28-CPU has been enhanced with the addition of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial safety certification. Device Information (1). PART NUMBER PACKAGE BODY SIZE.

8 F28M36P63C2 ZWT nFBGA (289) mm mm F28M36P53C2 ZWT nFBGA (289) mm mm F28M36H53C2 ZWT nFBGA (289) mm mm F28M36H33C2 ZWT nFBGA (289) mm mm (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. 2 Device Overview Copyright 2012 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2. F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2. F28M36H33C2, F28M36H33B2. SPRS825E OCTOBER 2012 REVISED DECEMBER 2017.

9 Functional Block Diagram SECURE C9-C15. C1. RAM RAM. GPIO_MUX1 VREG VREG 8KB 7 8KB. SECURE. (ECC) (parity). FLASH. BOOT 1MB SECURE C2-C8. USB+PHY (OTG). GP TIMER (4). NMI WDOG. ROM C0. WDOG (2). (ECC). UART (5). CAN (2). SSI (4). I C (2). EMAC. RAM RAM. uCRC. 2. EPI. 64KB 8KB 7 8KB. (ECC) (parity). APB BUS REGS. ONLY. AHB BUS. uDMA BUS. 12. ADC. 12 PINS. INPUTS ADC_1 M3 MPU. MODULE M3 BUS M3 CPU. AIO_MUX1. uDMA MATRIX NVIC. I-CODE BUS. D-CODE BUS. 6. COMP. INPUTS M3 SYSTEM BUS INTER- C28 CPU/DMA. PROC. ACCESS TO EPI. ANALOG COMMON INTERFACE BUS.

10 CLOCKS COMM. FREQ. RESETS GASKET. 6 MTOC CTOM. GPIO_MUX2. COMPARE S0 S1 S2 S3 S4 S5 S6 S7 MSG MSG. 6 + DAC MEM32. 8 PINS. NMI IPC RAM RAM. COMP UNITS TO AHB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB (parity) (parity). OUT BUS 2KB 2KB. PUTS DEBUG BRIDGE. S0-S7 SHARED RAM (parity). INTER- SECURITY PROC. 6 COMM. C28 DMA BUS. COMP. INPUTS. AIO_MUX2. C28 CPU. C28 C28 C28. 12 PINS. 12 ADC_2 DMA VCU FPU. MODULE PIE. ADC. INPUTS. C28 CPU BUS. ANALOG. SUBSYSTEM. 16- 32- 32- 16/32. BIT BIT BIT - BIT. PF2 PF1 PF3 PF0. BOOT SECURE L3 M1. EPWM (12). NMI WDOG. TIMER (3).