H-Bridge Gate Driver IC - NXP

1 MC33883H- bridge gate Driver ICRev. 27 April 2020 Data sheet: technical data SO20 1 General descriptionThe 33883 is an H-Bridge gate Driver (also known as a full- bridge pre- Driver ) IC withintegrated charge pump and independent high and low side gate Driver channels. Thegate Driver channels are independently controlled by four separate input pins, thusallowing the device to be optionally configured as two independent high side gate driversand two independent low side gate drivers . The low side channels are referenced toground. The high side channels are gate Driver outputs can source and sink up to A peak current pulses, permittinglarge gate -charge MOSFETs to be driven and/or high pulse- width modulation (PWM)frequencies to be utilized. A linear regulator is incorporated, providing a 15 V typical gatesupply to the low side gate drivers . The 33883 is AEC-Q100 device powered by SMARTMOS Features VCC operating voltage range from V up to 55 V VCC2 operating voltage range from V up to 28 V CMOS / LSTTL compatible I / O A peak gate Driver current Built-in high side charge pump Under- voltage lockout (UVLO) Over- voltage lockout (OVLO) Global enable with <10 A Sleep mode Supports PWM up to 100 kHz Qualified in compliance with AEC-Q100 NXP SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers.

2 NXP 2020. All rights sheet: technical dataRev. 27 April 20202 / 243 Simplified application diagramaaa-03737733883 MCUVCCVBATVBOOSTVCC2CP_OUTLR_OUTG_ENIN_H S1IN_LS1IN_HS2IN_LS2 GATE_HS1 SRC_HS1 GATE_LS1 DCMotorGATE_HS2 SRC_HS2 GATE_LS2 GND/2 GND_AC1C2 MFigure 1. Simplified application diagram4 Applications Automotive: 12 V to high - voltage battery packs E-bikes, e-scooters Energy Storage Systems (ESS) Uninterruptible Power supply (UPS) Battery junction box5 Ordering informationTable 1. Orderable part variationsPart number [1]VDDT emperature (TJ) to 55 V 40 C to 125 C20-pin 20 SOICW, pitch[1]To order parts in tape and reel, add the R2 suffix to the part SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers. NXP 2020. All rights sheet: technical dataRev. 27 April 20203 / 246 Internal block diagramaaa-026967 Figure 2. Internal block diagramNXP SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers.

3 NXP 2020. All rights sheet: technical dataRev. 27 April 20204 / 247 Pinning diagramaaa-037378 VCCC2CP_OUTSRC_HS1 GATE_HS1IN_HS1IN_LS1 GATE_LS1 GNDLR_OUT20191817161514131211G_ENSRC_HS2 GATE_LS2IN_HS2IN_LS2 GATE_LS2 GND2C1 GND_AVCC212345678910 Figure 3. Pinout definitionsFor a detailed description of each pin, see Section 9 "Functional description".Table 2. Pin definitionsPinnumberPin namePin functionDefinition1 VCCS upply voltage 1 Device power supply Pump CapacitorExternal capacitor for internal charge Pump OutExternal reservoir capacitor for internal charge 1 Output high SideSource of high -side 1 MOSFET5 GATE_HS 1 gate 1 Output high SideGate of high -side 1 high Side 1 Logicinput control of high -side 1 gate ( , IN_HS1 logic high = GATE_HS1 high ).7IN_LS1 Input Low Side 1 Logic input control of low-side 1 gate ( , IN_LS1 logic high = GATE_LS1 high ).8 GATE_LS1 gate 1 Output Low SideGate of low-side 1 1 Device ground Regulator OutputOutput of internal linear voltage 2 Device power supply GroundDevice analog Pump CapacitorExternal capacitor for internal charge 2 Device ground 2 Output Low SideGate of low-side 2 Low Side 2 Logic input control of low-side 2 gate ( , IN_LS2 logic high = GATE_LS2 high ).

4 17IN_HS2 Input high Side 2 Logicinput control of high -side 2 gate ( , IN_HS2 logic high = GATE_HS2 high ).18 GATE_HS 2 gate 2 Output high SideGate of high -side 2 2 Output high SideSource of high -side 2 SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers. NXP 2020. All rights sheet: technical dataRev. 27 April 20205 / 24 PinnumberPin namePin functionDefinition20G_ENGlobal EnableLogic input Enable control of device ( , G_EN logic high = Full Operation, G_EN logic LOW = Sleep Mode).8 General product ratingsTable 3. Maximum ratingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction orpermanent damage to the voltage 1 VCC to 65 VSupply voltage 2 (1)VCC2[1] to 35 VLinear Regulator Output VoltageVLR_OUT to 18 VHigh-Side Floating supply Absolute VoltageVCP_OUT to 65 VHigh-Side Floating Source VoltageVSRC_HS to 65 VHigh-Side Source Current from CP_OUT in Switch ON StateIS250mAHigh-Side gate VoltageVGATE_HS to 65 VHigh-Side gate Source voltage (2)VGATE_HS - VSRC_HS[2] to 20 VHigh-Side Floating supply gate VoltageVCP_OUT VGATE_HS to 65 VLow-Side gate VoltageVGATE_LS to 17 VWake-Up VoltageVG_EN to 35 VLogic Input VoltageVIN to 10 VCharge Pump Capacitor VoltageVC1 to VLR_OUTVC harge Pump Capacitor VoltageVC2 to 65 VESD VoltageHuman Body Model on All Pins (VCC and VCC2 as Two PowerSupplies)Machine Model VESD1 VESD2[3] 1500 130V[1]VCC2 can sustain load dump pulse of 40 V, 400 ms.

5 [2]In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown inFigure 14.[3]ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with theMachine Model (CZAP = 200 pF, RZAP = 0 ). electrical characteristicsTable 4. Static electrical characteristicsCharacteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = V unless otherwise values noted reflect the approximate parameter means at TA = 25 C under nominal conditions unless conditionsVCCS upply voltage 1 for Output high -Side Driver and Charge 55 VVCC2 supply voltage 2 for Linear 28 VNXP SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers. NXP 2020. All rights sheet: technical dataRev. 27 April 20206 / 24 SymbolParameterMinTypMaxUnitVCP_OUTHigh- Side Floating supply Absolute VoltageVCC + 4 VCC + 11but < 65 VLogicVIHL ogic 1 Input voltage (IN_LS and IN_HS) 10 VVILL ogic 0 Input voltage (IN_LS and IN_HS) +Logic 1 Input CurrentVIN = V 200 1000 AVG_ENWake-Up Input voltage (G_EN) Input Current (G_EN)VG_EN = 14 V 200 500 AIG_EN2 Wake-Up Input Current (G_EN)

6 VG_EN = 28 V regulatorVLR_OUTL inear regulatorVLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to20 mAVLR_OUT @ ILOAD = 20 mAVLR_OUT @ ILOAD = 20 mA, VCC2 = V, VCC = V VCC2 VCharge pumpVCP_OUTC harge Pump Output voltage , Reference to VCCVCC = 12 V, ILOAD = 0 mA, CCP_OUT = FVCC = 12 V, ILOAD = mA, CCP_OUT = FVCC2 = VCC = V, ILOAD = 0 mA, CCP_OUT = FVCC2 = VCC = V, ILOAD = mA, CCP_OUT = FVCC = 55 V, ILOAD = 0 mA, CCP_OUT = FVCC = 55 V, ILOAD = mA, CCP_OUT = F VIC1 Peak Current Through Pin C1 Under Rapidly Changing VCCV oltages (see Figure 13) Peak voltage at Pin C1 Under Rapidly Changing VCCV oltages (see Figure 13) VSupply voltageIVCCSLEEPQ uiescent VCC supply CurrentVG_EN = 0 V and VCC = 55 VVG_EN = 0 V and VCC = 12 V 1010 AIVCCOPO perating VCC supply CurrentVCC = 55 V and VCC2 = 28 VVCC = 12 V and VCC2 = 12 V[1] mAIVCCLOGA dditional Operating VCC supply Current for Each Logic InputPin ActiveVCC = 55 V and VCC2 = 28 V[2] VCC2 supply CurrentVG_EN = 0 V and VCC = 12 VVG_EN = 0 V and VCC = 28 V VCC2 supply CurrentVCC = 55 V and VCC2 = 28 VVCC = 12 V and VCC2 = 12 V[1] SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers.

7 NXP 2020. All rights sheet: technical dataRev. 27 April 20207 / 24 SymbolParameterMinTypMaxUnitIVCC2 LOGA dditional Operating VCC2 supply Current for Each Logic InputPin ActiveVCC = 55 V and VCC2 = 28 V[2] Shutdown Shutdown VCC2[3] Shutdown VCC576165 VOV2 Overvoltage Shutdown Sink Resistance (Turned Off)Idischarge LSS = 50 mA, VSRC_HS = 0 V[3] 22 RDSO utput Source Resistance (Turned On)Icharge HSS = 50 mA, VCP_OUT = 20 V[3] 22 ICHARGE HSSC harge Current of the External high -Side MOSFET ThroughGATE_HSn Pin[4] 100 200mAVMAXM aximum voltage (VGATE_HS - VSRC_HS)INH = Logic 1, ISmax = mA 18V[1]Logic input pin inactive ( high impedance).[2] high -frequency PWM-ing ( 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within thepackage power handling rating.[3]The device may exhibit predictable behavior between V and V.[4]See Figure 5 for a description of charge electrical characteristicsTable 5.

8 Dynamic electrical characteristicsCharacteristics noted under conditions V VSUP 18 V, 40 C TA 125 C, GND = V unless otherwise values noted reflect the approximate parameter means at TA = 25 C under nominal conditions unless characteristicstPDPropagation Delay high Side and Low SideCLOAD = nF, Between 50% Input to 50% Output(see Figure 4)[1] 200 300nstRTurn-On Rise TimeCLOAD = nF, 10% to 90%, (see Figure 4)[1] [2] 80 180nstFTurn-Off Fall TimeCLOAD = nF, 10% to 90%, (see Figure 4)[1] [2] 80 180ns[1]CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.[2]Rise time is given by time needed to change the gate from V to 10 V (vice versa for fall time).NXP SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers. NXP 2020. All rights sheet: technical dataRev. 27 April 20208 / diagram50%50%50%IN_HSorIN_LSGATE_HSorGAT E_LS50%tpdtrtfaaa-037380tpdFigure 4.

9 Timing characteristics9 Functional 33883 is an H-Bridge gate Driver (or full- bridge pre- Driver ) with integrated chargepump and independent high - and low-side Driver channels. It has the capability to drivelarge gate -charge MOSFETs and supports high PWM frequency. In sleep mode itssupply current is very pin voltage pins (VCC and VCC2)The VCC and VCC2 pins are the power supply inputs to the device. VCC is used for theoutput high -side drivers and the charge pump. VCC2 is used for the linear can be connected together or independent with different voltage values. The devicecan operate with VCC up to 55 V and VCC2 up to 28 VCC and VCC2 pins have undervoltage (UV) and overvoltage (OV) shutdown. Ifone of the supply voltage drops below the undervoltage threshold or rises above theovervoltage threshold, the gate outputs are switched LOW in order to switch off theexternal MOSFETs. When the supply returns to a level that is above the UV thresholdor below the OV threshold, the device resumes normal operation according to theestablished condition of the input high -side and low-side pins (IN_HS1, IN_HS2, IN_LS1, IN_LS2)The IN_HSn and IN_LSn pins are input control pins used to control the gate pins are V CMOS-compatible inputs with hysteresis.

10 IN_HSn and IN_LSnindependently control GATE_HSn and GATE_LSn, wake-up, the logic is supplied from the G_EN pin. There is no internal circuit toprevent the external high -side and low-side MOSFETs from conducting at the same output high -side pins (SRC_HS1 and SRC_HS2)The SRC_HSn pins are the sources of the external high -side MOSFETs. The externalhigh-side MOSFETs are controlled using the IN_HSn SemiconductorsMC33883H- bridge gate Driver ICMC33883 All information provided in this document is subject to legal disclaimers. NXP 2020. All rights sheet: technical dataRev. 27 April 20209 / high -side and low-side pins (GATE_HS1, GATE_HS2, GATE_LS1,GATE_LS2)The GATE_HSn and GATE_LSn pins are the gates of the external high - and low-sideMOSFETs. The external high - and low-side MOSFETs are controlled using the IN_HSnand IN_LSn enable (G_EN)The G_EN pin is used to place the device in a sleep mode. When the G_EN pin voltageis a logic LOW state, the device is in sleep mode.