Transcription of 第一部分：了解版图 - iczhiku.com
1 1. 2. 3. 4. 1. 2. 3. 4. 5. 1. 2. 1. 2. 3. 4. 5. 6. 8. 1. 2. 3. 4. 1. VDDGNDINOUT3 2. 1 2 3. Cadence Virtuoso Dracula Assura Diva Mentor calibre Spring soft laker DRC/LVS GDSII to FAB .tf .display Design rule DRC LVS PDK ESD 1. 2. 3. 4. 5. Poly M1 CT M2 1. 2. MOS.
2 MOS NMOS PMOS MOS MOS NMOS NMOS MOS 1) NMOS TSMC CMOS N NMOS P P N 2) NIMP N+ DIFF Poly M1 CONT 3) MOS 4) PCELL ; PCELL NMOS MOS 1) NMOS TSMC CMOS N PMOS N N P 2) NWELL N PIMP P+ DIFF Poly M1 CONT 3) MOS PMOS MOS 1) 2)NMOS PMOS 3) 4) Butting Contact VDDGNDINOUT3 W L R=L/W*R0 1) C=L*W*C0 2) poly MIM MOS C=W*L*Cox MIM MOS.
3 1) M1 M2 M3 2) Via1 Via2 1) CMOS N 1P4M LIBRARY 3. 1) virtuoso CIW 3. 2) virtuoso --Library manager CIW 3. 3) virtuoso -- cell 3. 4) virtuoso -- LSW 3. 5) virtuoso -- LSW 3. 6) virtuoso -- 3. 7) virtuoso -- 3. 8) virtuoso -- 3. 9) virtuoso -- 4. 1) virtuoso -- 4. 2) virtuoso -- 4. 3) virtuoso -- 4. 4) virtuoso -- SYMBOL VIEW Symbol 4. 5) virtuoso -- SYMBOL 4. 6) virtuoso --CDL 4. 7) virtuoso --CDL 5. SMIC -- CSMC TSMC -- UMC -- Winbond -- NEC.
4 1. 2. 1. PDK *.tf DRC LVS .cdsenv .cdsinit 2. N DIFF Poly Metal Cont Via .. 2. 1) PMOS 2. 2) PCELL 2. 3) Design Rule 2. 4) 2. 4) NW N WELL 2. 4) PO(Poly) 2. 4) M1(Metal1) 2. 4) VIA 3. DRC DRC:Design Rule Check DRC 5/1000= DRC 3. DRC nwell DRC NW DRC 4. LVS LVS: layout versus schematic LVS 4. LVS Environment setting 1) 2) LVS LVS LVS ERC LVS LVS COMPARE CASE NAMES SOURCE CASE YES LAYOUT CASE YES 4. LVS layer mapping: 1) gds 2) Map 4.
5 LVS Logic operation: 4. LVS DefinedDevices: 4. LVS Check tolerance: 1% 4. LVS LVS 4. LVS LVS Calibre Back 1. 2. 3. MOS 4. 5. 6. 8. 1. 1) 2) EDA 1) 2) Astro appollo 2. 3. 1 2 3.
6 1 2 3 CMP 1 2 3. 1 2 MOS 3 4 5 6 7 8 DUMMY DUMMY 3. MOS 3. MOS 1 3. MOS 2 finger AABBAABB ABBAABBA 3. MOS 3 MOS 3. MOS 4 3. MOS 5 3. MOS 6 coms MOS 7 8 3.
7 3. -- 3. 3. 1 2 4 8 16 1 2 4 8 16 3. 1 2 3 4 5 6 7 8 9 10 11 12 4. 1 2 3 4 5 1 2 3 4 M1 M4 M3 M2 1 2 3 4 5 6 1 drop 2 1 2um 10mv IR Drop 10mv 5 3 50 = / = 4 19 38 19 / 1 2 M1M2M3
8 1/3 CMOS finger 1 / 2 PN 1. Latch up cmos , power VDD GND PNP NPN BJT , VDD GND 2. Latch up I/O , 3. IC , , Latch up 4. Latch up , Latch up IC Layout 5. Latch up ( ) CMOS INV BJT BJT SCR B c 6. Latch up ( ) Q1 PNP BJT, (base) nwell, (collector) Q2 NPN BJT P substrate Rwell nwell Rsub substrate SCR BJT C-B Latch up BJT BJT BJT VDD GND Latch up 7. latch up P N 30-40u PAD MOS D MOS D AA 2u clk PLL ESD core cell latch up 40-50u 5.
9 1 2 1 2 3 4 M2 M1 M2 M3 M2 M2 5 1 2 3 4 5 6 7. 1 pad 2 3 4 5 6 7 8.
10 ESD ( 1 ESD -- ; -- ; -- ; 2 ~2KV PAD MOS gate 9. 1 2 45 Thank you! Q&A! IC)
