Interface Circuits for TIA/EIA-644 (LVDS) (Rev. B)

1 Design Notes September 2002 Mixed-Signal Products SLLA038B. IMPORTANT NOTICE. Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI. deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design.

2 Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.

3 Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303. Dallas, Texas 75265. Copyright 2002, Texas Instruments Incorporated Contents General Information .. 1. Electrical Characteristics .. 2. Driver .. 2. Receiver .. 4. Supply Voltage .. 5. Interconnections .. 6. Configurations .. 6. Characteristic Impedance of Media .. 6. Transmission Distance vs Signaling Rates .. 7. Line Termination .. 8. Skew, Balance, and ISI .. 8. Noise Immunity .. 9. Fail-Safe Operation .. 9. Radiated Emissions and Susceptibility.

4 9. Electrostatic Discharge .. 10. Eye Patterns .. 10. Setting Up the Eye Pattern .. 10. Taking Measurements From Eye Patterns .. 11. References .. 12. List of Figures 1 Typical Connection With LVDS Drivers and Receivers .. 2. 2 Driver and Receiver Electrical Characteristics .. 3. 3 Typical PCB Construction .. 4. 4 Typical Application Circuit Schematic for the SN65 LVDS31 and SN65 LVDS3487 Driver .. 5. 5 Typical Application Circuit Schematic for the SN65 LVDS32 and SN65 LVDS3486 Receiver .. 5. 6 Point-to-Point Configuration .. 6. 7 Multidrop Configuration .. 6. 8 Typical Transmission Distance vs Signaling Rates .. 7. 9 Differential Termination .. 8. 10 Open-Circuit Fail Safe of the LVDS Receiver .. 9. 11 Signal Distortion Using Eye Patterns .. 11. 12 Eye Pattern Oscilloscope Trace .. 11. 13 Measuring Signal Transmission Quality .. 12. iii iv SLLA038A. Interface Circuits for TIA/EIA-644 (LVDS). ABSTRACT. This design note provides information concerning the designing of TIA/EIA-644 Interface Circuits .

5 The TIA/EIA-644 standard is discussed including electrical characteristics, interconnections, line termination, and noise immunity. Finally, eye patterns are used to measure the effects of signal distortion, noise, signal attenuation, and the resultant intersymbol interference (ISI) in a data transmission system. General Information TIA/EIA-644 , otherwise known as LVDS, is a signaling method used for high-speed, low-power transmission of binary data over copper. This signaling technique uses lower output-voltage levels than the 5-V differential standards (such as TIA/EIA-422) to reduce power consumption, increase switching speed, and allow operation with a supply rail. The LVDS current-mode drivers create a differential voltage (247 mV to 454 mV) across a 100- load. The LVDS. receivers detect signals as low as 100 mV with as much as 1-V ground noise. TI offers LVDS receivers capable of recovering data over a common mode range from 4 V to 5 V, which allows up to 3 V of ground noise.

6 These receivers are designated SN65 LVDS33 and SN65 LVDS34. The standard specifies a theoretical maximum of Gbit/s. The intended application of this signaling technique is for baseband data transmission over controlled impedance media of approximately 100 , where the transmission media may be printed-circuit board (PCB) traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling from the environment. Figure 1 shows a typical connection with LVDS drivers and receivers. The data inputs to the quad driver are received at the Interface of the PCB traces from the host controller. The data inputs consist of up to n+1 bits of information and a transmit (Tx) clock. The data and clock signals are then transmitted differentially to the Interface of the quad driver outputs, to the interconnecting traces, and to the host PCB connector. The signals then propagate from the Interface of the host PCB connector to the cable connector to the balanced interconnecting media.

7 At the plug on the other end of the cable, the signals pass through the cable plug, the target connector Interface , and then to the target PCB traces. The LVDS. signal path ends at the Interface of the target PCB traces and the termination circuit. An additional Interface is located at the points where the PCB traces to the quad receiver inputs are connected. The outputs of the receiver Interface to the target PCB traces and then on to the receiving controller. 1. Host Power Balanced Interconnect Power Target Host Target Controller DBn DBn Controller DBn 1 DBn 1. DBn 2 DBn 2. DBn 3 DBn 3. DB2 DB2. DB1 DB1. DB0 DB0. TX Clock RX Clock SN65 LVDS31 SN65 LVDS32. Indicates twisting of the conductors. Indicates the line-termination circuit. Figure 1. Typical Connection With LVDS Drivers and Receivers Electrical Characteristics Driver The LVDS driver produces a differential voltage across a 100- load in the range of 247 mV to 454 mV with a typical offset voltage of V relative to ground (see Figure 2).

8 Most drivers are commonly implemented as current-mode devices, which allow power consumption to be virtually independent of frequency. These two characteristics, low voltage swings and constant current, allow LVDS drivers to operate at higher data rates and lower power dissipation. 2 SLLA038B. V. Common-Mode 100 mV. Voltage Receiver V Sensitivity Levels 100 mV. 2V. Common-Mode 247 454 mV Voltage 1 V Ground Noise V. V. DRIVER OUTPUT LEVELS 100 mV. Common-Mode Receiver Voltage Sensitivity Levels V. 100 mV. 0V. RECEIVER INPUT LEVELS. Figure 2. Driver and Receiver Electrical Characteristics Unused Pins Unused data input pins to the LVDS driver should be left open circuited, with the exception of the enabling pins. All inputs to the LVDS driver are internally pulled down to ground with approximately 300-k resistance. If the enable pins are not driven, they can be connected directly to VCC or GND. If there is a need for a pullup or pulldown resistor, then a resistance of no more than 10 k.

9 Is recommended. Board Traces All board traces from the host controller to the driver and from the driver to the connector should be as short as possible and matched in length. The overall length of any trace between the controller and driver should be kept to less than 5 cm and the lengths of all the traces to the controller should be matched to within 1 cm of each other with a 4-mA output buffer on the controller. Longer lengths are possible with higher current output buffers. The length of each trace between the driver outputs and the connector should be matched to within 5 mm of each other. Usually, this requires mitering the traces. If the PCB trace is more than 2 cm in length between the driver output pins and the connector, the PCB must be constructed to maintain a controlled differential impedance near 100 (see Figure 3). Interface Circuits for TIA/EIA-644 (LVDS) 3. 0,30 0,36 0,30 0,30 0,36 0,30.. 1,2 0,22 TYP. LAYER 1 (Signal). Single Pair LAYER 2 (Ground). Not Recommended LAYER 3 (Signal).

10 LAYER 4 (Signal) . Not Recommended NOTES: A. All fabrication items must meet or exceed best industry practice. B. Laminate material: copper-clad FR-4. C. Copper weight: 1 oz. start D. Finished board thickness: ( ) inch E. Dielectric thickness to be symmetrical between all layers ( inch). F. Maximum warp and twist: inch per inch G. Circuitry on outer layers to be tin-lead plated (60/40), plated to 300 in (minimum). H. Soldermask both sides per artwork: green enthone I. Copper plating to be inch (minimum) in plated-through holes J. Soldermask over bare copper with tin-lead hot-air leveling K. Dimensions are shown in millimeters Figure 3. Typical PCB Construction Receiver The recommended voltage applied to the receiver is between ground and V. with a common mode range of V to V. The receiver has a sensitivity level of 100 mV to correctly assume the intended binary state (see Figure 2). The LVDS interconnecting media must be matched with the 100- termination resistor located at the inputs of the receiver.