IS42S83200G, IS42S16160G IS45S83200G, IS45S16160G

1 is42s83200g , IS42S16160G is45s83200g , IS45S16160 GIntegrated Silicon Solution, Inc. 1 Rev. F12/9/2013 Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for Silicon Solution, Inc.

2 Does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:a.) the risk of injury or damage has been minimized;b.) the user assume all such risks; andc.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances FEATURES Clock frequency: 200,166, 143 MHz Fully synchronous.

3 All signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single Power supply: + LVTTL interface Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8K refresh cycles every 32 ms (A2 grade) or 64 ms (commercial, industrial, A1 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge commandOPTIONS Package: 54-pin TSOP-II 54-ball BGA Operating Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade A1 (-40oC to +85oC) Automotive Grade A2 (-40oC to +105oC)OVERVIEWISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture.

4 All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. 32 Meg x 8, 16 Meg x16 256Mb SYNCHRONOUS DRAMDECEMBER 2013IS42S83200G IS42S16160G 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII54-ball BGA 54-ball BGA Parameter32M x 8 16M x 16 Configuration8M x 8 x 4 banks4M x 16 x 4 banksRefresh Count AddressesA0-A12A0-A12 Column AddressesA0-A9A0-A8 Bank Address PinsBA0, BA1BA0, BA1 Auto Precharge PinsA10/APA10/APADDRESS TABLEKEY TIMING PARAMETERSP arameter -5 -6 -7 UnitClk Cycle Time CAS Latency = 3 5 6 7 ns CAS Latency = 2 10 10 nsClk Frequency CAS Latency = 3 200 166 143 Mhz CAS Latency = 2 100 100 133 MhzAccess Time from Clock CAS Latency = 3 5 ns CAS Latency = 2 5 ns2 Integrated Silicon Solution, Inc.

5 Rev. F12/9/2013IS42S83200G, IS42S16160 GIS45S83200G, IS45S16160 GDEVICE OVERVIEWThe 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in Vdd and Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is orga-nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK.

6 All inputs and outputs are LVTTL 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence.

7 The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. CLKCKECSRASCASWEA9A8A7A6A5A4A3A2A1A0BA0B A1A10A12 COMMANDDECODER&CLOCKGENERATORMODEREGISTE RREFRESHCONTROLLERREFRESHCOUNTER SELFREFRESHCONTROLLERROWADDRESSLATCHMULT IPLEXERCOLUMNADDRESS LATCHBURST COUNTERCOLUMNADDRESS BUFFERCOLUMN DECODERDATA INBUFFERDATA OUTBUFFERDQML DQMHDQ 0-15 VDD/VDDQVss/VssQ131391313 916161616512(x 16)819281928192 ROW DECODER8192 MEMORY CELLARRAYBANK 0 SENSE AMP I/O GATEBANK CONTROL LOGICROWADDRESSBUFFERA112 FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx16x4 BANKS SHOWN)Integrated Silicon Solution, Inc.

8 3 Rev. F12/9/2013IS42S83200G, IS42S16160 GIS45S83200G, IS45S16160 GVDDDQ0 VDDQNCDQ1 VSSQNCDQ2 VDDQNCDQ3 VSSQNCVDDNCWECASRASCSBA0BA1A10A0A1A2A3 VDD1234567891011121314151617181920212223 2425262754535251504948474645444342414039 3837363534333231302928 VSSDQ7 VSSQ NCDQ6 VDDQNCDQ5 VSSQNCDQ4 VDDQNCVSSNCDQMCLKCKEA12A11 A9 A8A7 A6A5A4 VSSPIN CONFIGURATIONS54 pin TSOP - Type II for x8 PIN DESCRIPTIONSA0-A12 Row Address InputA0-A9 Column Address InputBA0, BA1 Bank Select AddressDQ0 to DQ7 Data I/OCLK System Clock InputCKE Clock EnableCS Chip SelectRAS Row Address Strobe CommandCAS Column Address Strobe CommandWE Write EnableDQM Data Input/Output MaskVdd PowerVss GroundVddq Power Supply for I/O PinVssq Ground for I/O PinNC No Connection4 Integrated Silicon Solution, Inc.

9 Rev. F12/9/2013IS42S83200G, IS42S16160 GIS45S83200G, IS45S16160 GPIN CONFIGURATIONS54 pin TSOP - Type II for x16 PIN DESCRIPTIONSA0-A12 Row Address InputA0-A8 Column Address InputBA0, BA1 Bank Select AddressDQ0 to DQ15 Data I/OCLK System Clock InputCKE Clock EnableCS Chip SelectRAS Row Address Strobe CommandCAS Column Address Strobe CommandVDDDQ0 VDDQDQ1DQ2 VSSQDQ3DQ4 VDDQDQ5DQ6 VSSQDQ7 VDDDQMLWECASRASCSBA0BA1A10A0A1A2A3 VDD1234567891011121314151617181920212223 2425262754535251504948474645444342414039 3837363534333231302928 VSSDQ15 VSSQ DQ14 DQ13 VDDQDQ12DQ11 VSSQDQ10DQ9 VDDQDQ8 VSSNCDQMHCLKCKEA12A11 A9 A8A7 A6A5A4 VSSWE Write EnableDQML x16 Lower Byte, Input/Output MaskDQMH x16 Upper Byte.

10 Input/Output MaskVdd PowerVss GroundVddq Power Supply for I/O PinVssq Ground for I/O PinNC No ConnectionIntegrated Silicon Solution, Inc. 5 Rev. F12/9/2013IS42S83200G, IS42S16160 GIS45S83200G, IS45S16160 GPIN CONFIGURATION54-ball TF-BGA for x8 (Top View) ( mm x mm Body, mm Ball Pitch)package code: B 1 2 3 4 5 6 7 8 9 ABCDEFGHJVSSA12A8 VSSNCCLKA11A7A5 VSSQVDDQVSSQVDDQVSSCKEA9A6A4 VDDQVSSQVDDQVSSQVDDCASBA0A0A3DQ0 RASBA1A1A2 VDDWECSA10 VDDPIN DESCRIPTIONSA0-A12 Row Address InputA0-A9 Column Address InputBA0, BA1 Bank Select AddressDQ0 to DQ7 Data I/OCLK System Clock InputCKE Clock EnableCS Chip SelectRAS Row Address Strobe CommandCAS Column Address Strobe CommandWE Write EnableDQM Data Input/Output MaskVdd PowerVss GroundVddq Power Supply for I/O PinVssq Ground for I/O PinNC No ConnectionNCNCNCNCDQMDQ7DQ6DQ5DQ4 NCNCNCNCNCDQ1DQ2DQ36 Integrated Silicon Solution.