MCP4801/4811/4821 Data Sheet - Microchip Technology

1 2010 Microchip Technology 1 MCP4801/4811/4821 Features mcp4801 : 8-Bit Voltage Output DAC MCP4811: 10-Bit Voltage Output DAC MCP4821: 12-Bit Voltage Output DAC Rail-to-Rail Output SPI Interface with 20 MHz Clock Support Simultaneous Latching of the DAC Output with LDAC Pin Fast Settling Time of s Selectable Unity or 2x Gain Output Internal Voltage Reference 50ppm/ C VREF Temperature Coefficient to Single-Supply Operation Extended Temperature Range: -40 C to +125 CApplications Set Point or Offset Trimming Sensor Calibration Precision Selectable Voltage Reference Portable Instrumentation (Battery-Powered) Calibration of Optical Communication DevicesDescriptionThe MCP4801/4811/4821 devices are single channel8-bit, 10-bit and 12-bit buffered voltage outputDigital-to-Analog Converters (DACs), respectively.

2 Thedevices operate from a single to supply withan SPI compatible Serial Peripheral Interface. The devices have a high precision internal voltagereference (VREF = ). The user can configure thefull-scale range of the device to be or bysetting the Gain Selection Option bit (gain of 1 of 2).The devices can be operated in Active or Shutdownmode by setting a Configuration register bit or using theSHDN pin. In Shutdown mode, most of the internalcircuits, including the output amplifier, are turned off forpower savings, while the amplifier output (VOUT) stage isconfigured to present a known high resistance outputload (500 k typical . The devices include double-buffered registers,allowing a synchronous update of the DAC outputusing the LDAC pin.)

3 These devices also incorporate aPower-on Reset (POR) circuit to ensure reliable devices utilize a resistive string architecture, withits inherent advantages of low DNL error, low ratiometric temperature coefficient and fast settling devices are specified over the extendedtemperature range (+125 C). The devices provide high accuracy and low noiseperformance for consumer and industrial applicationswhere calibration or compensation of signals (such astemperature, pressure and humidity) are required. The MCP4801/4811/4821 devices are available in thePDIP, SOIC, MSOP and DFN packages. Related Products(1)P/NDAC ResolutionNo. of ChannelVoltage Reference(VREF)MCP480181 Internal( )MCP4811101 MCP4821121 MCP480282 MCP4812102 MCP4822122 MCP490181 ExternalMCP4911101 MCP4921121 MCP490282 MCP4912102 MCP4922122 Note 1:The products listed here have similarAC/DC performances.

4 8/10/12-Bit Voltage Output Digital-to-Analog Converterwith Internal VREF and SPI InterfaceMCP4801/4811/4821DS22244B-page 2 2010 Microchip Technology TypesBlock DiagramDFN (2x3)*12348765 CSSCKSDIVDDVSSVOUTSHDNLDACMCP4801: 8-bit single DACMCP4811: 10-bit single DACMCP4821: 12-bit single DACMCP48X1 PDIP, SOIC, MSOP12348765 CSSCKSDIVDDVSSVOUTSHDNLDAC9* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - AmpVDDVSSCSSDISCKI nterface LogicInput RegisterDAC RegisterStringDACP ower-on ResetVOUTLDACO utputGainLogic( )SHDNVREFO utputLogic 2010 Microchip Technology 3 mcp4801 /4811 CHARACTERISTICSA bsolute Maximum Ratings inputs and outputs ..VSS to VDD + Current at Input Pins .. 2 mACurrent at Supply Pins .. 50 mACurrent at Output Pins .. 25 mAStorage temperature ..-65 C to +150 CAmbient temp.

5 With power applied ..-55 C to +125 CESD protection on all pins 4 kV (HBM), 400V (MM)Maximum Junction Temperature (TJ) ..+150 C Notice: Stresses above those listed under MaximumRatings may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperational listings of this specification is not to maximum rating conditions for extended periodsmay affect device CHARACTERISTICSE lectrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = , Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85 C. Typical values are at +25 RequirementsOperating CurrentIDD 330400 AAll digital inputs are grounded, analog output (VOUT) is unloaded.

6 Code = 000hHardware Shutdown CurrentISHDN APOR circuit is turned offSoftware Shutdown CurrentISHDN_SW APOR circuit remains turned onPower-on Reset ThresholdVPOR VDC AccuracyMCP4801 Resolutionn8 BitsINL ErrorINL-1 + 1 MCP4811 Resolutionn10 BitsINL + 1 MCP4821 Resolutionn12 BitsINL ErrorINL-12 212 LSbDNL + 1 Offset ErrorVOS-1 of FSR Code = 0x000hOffset Error TemperatureCoefficientVOS/ C ppm/ C-45 C to +25 C ppm/ C+25 C to +85 CGain Error of FSR Code = 0xFFFh, not including offset errorGain Error Temperature Coefficient G/ C -3 ppm/ CNote 1:Guaranteed monotonic by design over all :This parameter is ensured by design, and not 100% 4 2010 Microchip Technology Voltage Reference (VREF)Internal Reference when G = 1x andCode = 0xFFFhTemperature Coefficient(Note 2) VREF/ C 125325ppm/ C-40 C to 0 C C-40 C to 0 C 45160ppm/ C0 C to +85 C C0 C to +85 COutput Noise (VREF Noise)ENREF( Hz) 290 Vp-pCode = 0xFFFh, G = 1xOutput Noise DensityeNREF(1 kHz) V/ HzCode = 0xFFFh, G = 1xeNREF(10 kHz) V/ HzCode = 0xFFFh, G = 1x1/f Corner FrequencyfCORNER 400 HzOutput AmplifierOutput SwingVOUT toVDD VAccuracy is better than 1 LSb for VOUT = 10 mV to (VDD 40mV)Phase MarginPM 66 Degree ( )

7 CL = 400 pF, RL = Slew RateSR V/ sShort Circuit CurrentISC 1524mASettling TimetSETTLING sWithin LSb of final value from to full-scale rangeDynamic Performance (Note 2)Major Code Transition Glitch 45 nV-s1 LSb change around major carry ( to )Digital Feedthrough <10 nV-sELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = , Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85 C. Typical values are at +25 1:Guaranteed monotonic by design over all :This parameter is ensured by design, and not 100% tested. 2010 Microchip Technology 5 MCP4801/4811/4821 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATUREE lectrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = , Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF.

8 Typical values are at +125 C by characterization or RequirementsOperating CurrentIDD 350 AAll digital inputs are grounded, analog output (VOUT) is unloaded. Code = 000hHardware Shutdown CurrentISHDN APOR circuit is turned offSoftware Shutdown CurrentISHDN_SW 5 APOR circuit remains turned onPower-on Reset thresholdVPOR VDC AccuracyMCP4801 Resolutionn8 BitsINL ErrorINL LSbDNL DNL LSbNote 1 MCP4811 Resolutionn10 BitsINL ErrorINL 1 LSbDNL DNL LSbNote 1 MCP4821 Resolutionn12 BitsINL ErrorINL 4 LSbDNL DNL LSbNote 1 Offset ErrorVOS % of FSR Code = 0x000hOffset Error TemperatureCoefficientVOS/ C -5 ppm/ C+25 C to +125 CGain Error gE % of FSR Code = 0xFFFh, not including offset errorGain Error Temperature Coefficient G/ C -3 ppm/ CInternal Voltage Reference (VREF)Internal Reference VoltageVREF VVOUT when G = 1x andCode = 0xFFFhTemperature Coefficient (Note 2)

9 VREF/ C 125 ppm/ C-40 C to 0 C LSb/ C-40 C to 0 C 45 ppm/ C0 C to +85 C LSb/ C0 C to +85 COutput Noise (VREF Noise)ENREF( 10 Hz) 290 Vp-pCode = 0xFFFh, G = 1xOutput Noise DensityeNREF(1 kHz) V/ HzCode = 0xFFFh, G = 1xeNREF(10 kHz) V/ HzCode = 0xFFFh, G = 1x1/f Corner FrequencyfCORNER 400 HzNote 1:Guaranteed monotonic by design over all :This parameter is ensured by design, and not 100% 6 2010 Microchip Technology AmplifierOutput SwingVOUT to VDD VAccuracy is better than 1 LSb for VOUT = 10 mV to (VDD 40 mV)Phase MarginPM 66 Degree ( ) CL = 400 pF, RL = Slew RateSR V/ sShort Circuit CurrentISC 17 mASettling TimetSETTLING sWithin LSb of final value from to full-scale rangeDynamic Performance (Note 2)Major Code Transition Glitch 45 nV-s1 LSb change around major carry ( to )Digital Feedthrough <10 nV-sAC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)Electrical Specifications: Unless otherwise indicated, VDD= , TA= -40 to +125 C.

10 Typical values are at +25 Trigger High-Level Input Voltage (All digital input pins) VDD VSchmitt Trigger Low-Level Input Voltage (All digital input pins)VIL of Schmitt Trigger InputsVHYS Input Leakage CurrentILEAKAGE-1 1 ASHDN = LDAC = CS = SDI = SCK = VDD or VSSD igital Pin Capacitance(All inputs/outputs)CIN, COUT 10 pFVDD = , TA = +25 C, fCLK = 1 MHz (Note 1)Clock FrequencyFCLK 20 MHzTA = +25 C (Note 1)Clock High TimetHI15 nsNote 1 Clock Low TimetLO15 nsNote 1CS Fall to First Rising CLK EdgetCSSR40 nsApplies only when CS falls with CLK high. (Note 1)Data Input Setup TimetSU15 nsNote 1 Data Input Hold TimetHD10 nsNote 1 SCK Rise to CS Rise Hold TimetCHS15 nsNote 1CS High Time tCSH15 nsNote 1 LDAC Pulse WidthtLD100 nsNote 1 LDAC Setup TimetLS40 nsNote 1 SCK Idle Time before CS Fall tIDLE40 nsNote 1 Note 1:This parameter is ensured by design and not 100% tested.