Latch-Up White Paper - Texas Instruments

1 1 SCAA124 April2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedLatch-U pWhitePaperSCAA124 April2015 Latch-UpMartyJohnson,RogerCline,ScottWar d,Joe SchichlABSTRACTT hisdocumentdescribesand discussesthe topicof CMOSL atch-Uprangingfromtheoryto JEDEC standardJESD78are discussedalongwithprogressfor makingit moreanalogfriendlywithrespectto specialpin of Figures1 Cross-Sectionof a April2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedLatch-U p(1)All trademarksare the propertyof theirrespectiveowners.(1)1 IntroductionLatch-Uptodayis still a potentiallypotentsourceof failurein the qualificationflow at manufacturersand inthe IC s get smaller,so do the dimensionsbetweentransistorswithinan createconditionsfor influencingthe industrytoconsidermorecompletemethodsto stressLatch-Upin all productsbut in particular, at TexasInstrumentsis to continuouslyimprovethe qualityand reliabilityof the Latch-Up ?

2 Latch-Upis a conditionwherea low impedancepathis createdbetweena supplypin and causedby a trigger(currentinjectionor overvoltage),but onceactivated,the low impedancepathremainsevenafterthe triggeris no low impedancepathmay causesystemupsetor catastrophicdamagedue to Latch-Upconditiontypicallyrequiresapower cycleto eliminatethe low BiCMOS circuitsuse NMOSand PMOS transistorsto createthe the designof the CMOS integratedcircuit,the proximityof thePN junctionsthat formthe NMOSand PMOS transistorscreateinherentparasitictransi storsand ,also calledsilicon-controlledrectifiers(SCRs) .Excursions(overshootsand undershoots)outsidethe normaloperatingvoltageand currentlevelscantriggerPNPNT hyristorsand may not a risk if the voltageand currentlevelsappliedto the deviceadhereto the CMOS development,Latch-Upwas recognizedas a problemto be the causesled to severalpapersin the 1980 s discussingcausesand methodsto lessenthe influenceof NMOSand PMOS circuitsformparasiticPNPN structuresthat can betriggeredwhena currentor voltageimpulseis directedinto an input,outputor showsa typical,simple,cross-sectionof a CMOS inverterin an N-Well,P- substrate, PMOS formsa parasiticverticalPNPfromthe P+ source/drainof the transistor(emitter),theN-Well(base)and the substrate(collector).

3 A lateralNPNis formedfromthe N+ source/drain(emitter),P-substrate(base)a nd the N-Well(collector).The resultantcircuitdescribesa PNPN(as shownin Figure2).As an example,if a currentimpulsestrikesthe PMOS drain,the P+/ N-Welljunction(Q1) the impulseis high enough(sustainablefor a sufficientlengthof time),the carriersinjectedinto the substratecausea voltagedropacrossthe bias acrossthe P- /N+ (substrateto NMOS drain)in Q2 is thenhigh enoughto turn-onQ2. The Q2 collectorcurrentwill thenflow into the baseof Q1. At that time,the Latch-Upbecomesself-sustaining,a positivefeedbackloop the powersupplycan stop the (externaland internalto the product)can also influencethe temperatureincreases,the substrateand well resistancesrise allowingthe bias to ,the effectivedistancebetweenthe N+, P+ and N-Welldiffusionsnarrowsallowingeasiercap tureof April2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedLatch-U pFigure1.

4 Cross-Sectionof a CMOSI nverterFigure2. methodsemployedto reducethe possibleonsetof the elementsof eachtransistor,diode,resistorand capacitorare now beingcontrolledthroughprocesscharacteriz ationanddesignrulesto help minimizethe effectof currentor voltagepulseson the ,guardringshavebeenaddedaroundknownradia torsin the circuitsor if spacingconcernsare criticalaroundindividualPMOSand NMOS transistors,diodesor as injectedcarriersyphonsallowingthesecarri ersto flow to the supplyor ,the use of substrateties and welltaps act as excitedcarriersyphonsand are guidedby designrulesfor and taps arenecessaryfor effectivemethodof quenchingLatch-Upis to use an EPI(epitaxialsilicon) EPI layeris dopedappropriatelyfor the best transistorperformance(morelightlydopedth anthe remaininglowerportionof the substratethat is highlydoped).

5 The highlydopedsubstratedirectsmajoritycarri ersto groundand reflectsminoritycarriersmakingthe guardringsmoreeffective(seeFigure3). Evenwith thesesafeguards,thereis a possibilityof parasitictransistorsin circuitsthat are not be identified;one way is a April2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedLatch-U pFigure3. Cross-SectionWithGuardRingsIncluded2 Latch-UpTestingMethodsLatch-Upstressmeth odspriorto the late 1980 s wereaccomplishedon benchset-upswith the use ofcurvetracersor 1988,an industryteamreleasedthe first Latch-Upstandard, standardproposeda methodof characterizationbasedmostlyon 1997,the JEDEC teamproposedanotherLatch-Upstandard(JESD 78)that built on JESD17addingmoredetailto the stressand givinga robustnesscriteriafor the first digitalCMOS technologyand test currentrevision,RevisionD,doesnot havea robustnesscriterion.

6 It has revertedto beinga not necessarilyfit well into the methodologysincethereare generallyspecificbias valuesthat workoutsidea zeroor one effortsunderwayon the JEDECL atch-Upteamto add analogmethodology,whichwill likelybe completedlate in currentLatch-Upstandard,JESD78,stressesp ins categorizedby input,output,bi-directional(I/O),powersu pplyand ,outputand bi-directionalpins,in mostcases,receivea powersupplyreceivesan over-voltagestress,a pulsewidthscan be chosenfroma rangeof valuesbut mostoftenin the industry,2 ms to 10 ms is currentpulseheighttypicalvaluesare 100 mA whilethe over-voltageis x VMAX(operating).Productsrequiringclockin gor othertimingsignalscan use test vectorsin eithera Latch-Uptesteror pins receivingvectorsgenerallyare not stressedsincethe stresspulsemay interferewiththe part set-upcreatinga , Figure5 and Figure6 showthe Measure nominal I(Inom)T4T7 Cool down time (Tcool)T4T5 Wait time prior to Imeasurement.

7 *T5 Measure IT6 If any Ithe failure criteria defined in , latch-uphas occurred and power must be removed from there supplysupplysupplysupply T1T2T3T4T5T6T7I triggertrtrTOSGNDVPIN supply90%Max. VsupplyTOSS tress current forcharacterization10%tfTimeOperationT1T 2 Measure nominal I(Inom)T4T7 Cool down time (Tcool)T4T5 Wait time prior to Imeasurement. *T5 Measure IT6 If any Ithe failure criteria defined in , latch-uphas occurred and power must be removed from DUT. supplysupplysupplysupply PIN UNDER TESTT1T2 T3T4 T5T6T7I triggertrtrTOSGNDVPIN supply90%Max. VsupplyMin. Logic Low **TOStfStress current forcharacterizationTimeOperationT1T2 Measure nominal I(Inom)T4T7 Cool down time (Tcool)T4T5 Wait time prior to Imeasurement.

8 *T5 Measure IT6 If any Ithe failure criteria defined in , latch-uphas occurred and power must be removed from DUT. supplysupplysupplysupply PIN UNDER TESTT1T2T3T4T5T6T7 GNDtrtftrTOSTOSGNDVPIN supplyStress current forcharacterizationTOS90%Max. VsupplyMax. Logic High **I April2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedLatch-U pFigure4. PositiveCurrentPulseWaveformFigure5. NegativeCurrentPulseWaveformFigure6. April2015 SubmitDocumentationFeedbackCopyright 2015, goal is to stressin everycombinationof inputbias conditionsandsubsequentoutputconditionst hat can be achievedwithoutdisruptingthe stabilityof the start,one needsto placethe productinto a known,stablestatethat has a ,all of the pins held high are exposedto a pins requiredto be low forproductstabilityare not inputsthat can switchto low are thenpulsedwith a negativepulseand any pin held high for stabilityis not be pins held high or low for stabilitythatcannottoleratea the outputconditionwill havea pulsedcurrentofthe high-Zconditionis preferred,if possible.

9 Sinceit givesthe opportunityto stressitwith bothpositiveand will needto be configuredin a over-voltagestresstest is set-upto determinethe abilityof the powersuppliesto digitalproducts,eachinputcondition(higha nd low) mustbe checkedby the over-voltagetest. The powersuppliesare thenstressedwith over-voltagevalueseitherat x VMAXor MSV(seeFigure6). the Latch-Updescriptionin , that definesa malfunctionof the IC, generally,ashortingof the powersupplyto ground,SignalLatch-Up(sLU)is also a malfunctionof the IC; however,ashortingof the signalto groundas opposedto the traditionalshortingof the powersupplyto detectedby a sustainedincreasein ISUPPLY afterthe applicablestressis manifestitselfin a sustainedincreasein ISUPPLY, but ratherdetectedin a sustainedincreasein ISIGNAL afterthe applicablestressin generallynot a problemassociatedwith normaloperation,SignalLatch-Upcan be a problemassociatedwith normaloperationdependingon the designof signalESDprotectionstructures,therecan beintentionalSCRsemployedthat encourageselectedparasiticPNPN diodesto triggerunderan an unpoweredevent,this is not a concernand ,duringnormaloperationsincean intentionalSCRcouldexistbetweena signalpin to groundand the signalpin couldbetied or drivento a hi state.

10 Caremustbe takenby usingdesignruleson the productto limit effectsofSignalLatch-Up,thereby,mitigati ngthe effectof excursionthat couldtriggerthe signalESDSCR andeffectivelyshortthe signalto a signalpin is tied or drivento a lo state,thenthe signalvoltageis belowthe ESDSCR holdingvoltageand signalLatch-Upwill not is notedin the Scopeof JESD78, As thesetechnologieshaveevolved,it has beennecessaryto adjustthis documentto the realitiesofcharacterizationwith limitsnot imaginedwhenthe first Latch-Updocumentwas generatedsome25 wouldbe simplerto makethe originallimitsof timesthe maximumpin operatingvoltagean absolutelevelof goodness,the possibilitiesof successat this levelare limitedby the very lowvoltagetechnologies,and the mediumand high voltageCMOS,BiCMOSand Bipolartechnologies(>40V). The conceptof maximumstressvoltage(MSV)allowsthe supplierto characterizeLatch-Upin a waythat differentiatesbetweenLatch-Upand revisionwill makeit moretransparentto the end userthat giventhe limitsof certaintechnologiesthe subsequentLatch-Upcharacterizationsare valid.