LIS2DW12 - st.com

1 Features Ultra-low power consumption: 50 nA in power-down mode, below 1 A in activelow-power mode Very low noise: down to mg RMS in low-power mode Multiple operating modes with multiple bandwidths Android stationary detection, motion detection Supply voltage, V to V Independent IO supply 2g/ 4g/ 8g/ 16g full scale High-speed I C/SPI digital output interface Single data conversion on demand 16-bit data output Embedded temperature sensor Self-test 32-level FIFO 10000 g high shock survivability ECOPACK , RoHS and Green compliantApplications motion detection for wearables Gesture recognition and gaming motion -activated functions and user interfaces Display orientation Tap/double-tap recognition Free-fall detection Smart power saving for handheld devices Hearing aids Portable healthcare devices Wireless sensor nodes motion -enabled metering devicesDescriptionThe LIS2DW12 is an ultra-low-power high-performance three-axis linearaccelerometer belonging to the femto family which leverages on the robust andmature manufacturing processes already used for the production of LIS2DW12 has user-selectable full scales of 2g/ 4g/ 8g/ 16g and is capable ofmeasuring

2 Accelerations with output data rates from Hz to 1600 LIS2DW12 has an integrated 32-level first-in, first-out (FIFO) buffer allowing theuser to store data in order to limit intervention by the host embedded self-test capability allows the user to check the functioning of thesensor in the final status linkLIS2DW12 Product summaryOrder codeLIS2DW12 LIS2DW12 TRTemperaturerange [ C]-40 to +85 PackageLGA-12 PackingTrayTape and reelProduct labelMEMS digital output motion sensor: high-performance ultra-low-power 3-axis "femto" accelerometerLIS2DW12 DatasheetDS11811 - Rev 6 - November 2018 For further information contact your local STMicroelectronics sales LIS2DW12 has a dedicated internal engine to process motion and accelerationdetection including free-fall, wakeup, highly configurable single/double-taprecognition, activity/inactivity, stationary/ motion detection, portrait/landscapedetection and 6D/4D LIS2DW12 is available in a small thin plastic land grid array package (LGA) andit is guaranteed to operate over an extended temperature range from -40 C to+85 - Rev 6page 2/651 Block diagram and pin diagramFigure 1.

3 Block diagramCHARGEAMPLIFIERY+Z+Y-Z-aX+X-I CSPICSSCL/SPCSDA/SDO/SDISDO/SA0 CONTROL LOGIC&INTERRUPT CLOCKTRIMMINGCIRCUITSREFERENCECONTROL A/D CONVERTERINT2 MUXLOGICSELF TEST 32 LevelFIFO TEMPERATURE SENSOR2 LIS2DW12 Block diagram and pin description DS11811 - Rev 6page 3 descriptionFigure 2. Pin connections198723465111210 GNDRESSCL/SPCCSSDO/SA0 SDA/SDI/SDONCINT2 INT1(TOPVIEW)DIRECTION OF THEDETECTABLEACCELERATIONSY1 XZVDD(BOTTOM VIEW)GNDVDDIOT able 1. Pin descriptionPin#NameFunction1 SCLSPCI C serial clock (SCL)SPI serial port clock (SPC)2(1)CSSPI enableI C/SPI mode selection(1: SPI idle mode / I C communication enabled;0: SPI communication mode / I C disabled)3(1)SDOSA0 SPI serial data output (SDO)I C less significant bit of the device address (SA0)4 SDASDISDOI C serial data (SDA)SPI serial data input (SDI)3-wire interface serial data output (SDO)5 NCInternally not connected.

4 Can be tied to VDD, VDDIO, or V supply7 RESC onnect to GND8 GND0 V supply9 VDDP ower supply10 VDD_IOPower supply for I/O pins11 INT2 Interrupt pin 2. Clock input when selected in single data conversion on pin 1 1. SDO/SA0 and CS pins are internally pulled up. Refer to Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pins forthe internal pull-up values (typ). LIS2DW12 Pin description DS11811 - Rev 6page 4/65 Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pinsVdd_IOResistor value for SDO/SA0 and CS pinsTyp. (k ) description DS11811 - Rev 6page 5/652 Mechanical and electrical characteristics@ Vdd = V, T = 25 C unless otherwise noted. The product is factory calibrated at V.

5 The operationalpower supply range is from V to 3. Mechanical characteristicsSymbolParameterTest (1) range 2g 4 8 16 SoSensitivity@ FS 2 g in High-Performance Mode and all low-powermodes except Low-Power Mode @ FS 4 g in High-Performance Mode and all low-powermodes except Low-Power Mode @ FS 8 g in High-Performance Mode and all low-powermodes except Low-Power Mode @ FS 16 g in High-Performance Mode and all low-power modes except Low-Power Mode @ FS 2 g in Low-Power Mode @ FS 4 g in Low-Power Mode @ FS 8 g in Low-Power Mode @ FS 16 g in Low-Power Mode density - High-performanceMode(2)@ FS 2 g90 g/ HzRMSRMS noise - Low-Power Modes(3)@ FS 2 gLow-Power Mode (RMS)Low-Power Mode Mode Mode level offset accuracy(4)

6 20mgTCOZero-g offset change vs. temperature CTCSS ensitivity change vs. CSTSelf-test positive difference701500mg 1. Typical specifications are not Noise density is the same for all ODRs. Low-noise setting RMS noise is the same for all ODRs. Low-noise setting Values after factory calibration test and trimming. LIS2DW12 Mechanical and electrical specifications DS11811 - Rev 6page 6 characteristics@ Vdd = V, T = 25 C unless otherwise noted. The product is factory calibrated at V. The operationalpower supply range is from V to 4. Electrical characteristicsSymbolParameterTest (1) pins supply voltage(2) + consumption in High-Performance Mode(3)@ ODR Hz - 1600 Hz, 14-bit90 AIddLPCurrent consumption in Low-Power Mode(4)ODR 100 Hz5 AODR 50 Hz3 ODR Hz1 ODR consumption in power-down50nAVIHD igital high-level input *Vdd_IOVVILD igital low-level input *Vdd_IOVVOHD igital high-level output voltageIOH = 4 mA(5)VDD_IO - VVVOLD igital low-level output voltageIOL = 4 mA(5) VV 1.

7 Typical specifications are not It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses. In thiscondition the measurement chain is powered Low-noise setting Low-Power Mode 1. Low-noise setting 4 mA is the maximum driving capability, ie. the maximum DC current that can be sourced/sunk by the digitalpad in order to guarantee the correct digital output voltage levels VOH and VOL. LIS2DW12 Electrical characteristics DS11811 - Rev 6page 7 sensor characteristics@ Vdd = V, T = 25 C unless otherwise notedTable 5. Temperature sensor (1) temperature range-40+85 CToffTemperature offset(2)-15+15 CTSDrTemperature sensor output change vs. temperature1(3)LSB/ C16(4)TODRT emperature refresh rate in High-Performance Mode for all ODRsor in low-power modes for ODRs equal to 200/100/50 Hz50 HzTemperature refresh rate in low-power modes for ODR equal to 25 Hz25 Temperature refresh rate in low-power modes for ODR equal to refresh rate in low-power modes for ODR equal to 1.

8 Typical specifications are not The output of the temperature sensor is 0 LSB (typ.) at 25 8-bit 12-bit resolution. LIS2DW12 Temperature sensor characteristics DS11811 - Rev 6page 8 interface - serial peripheral interfaceSubject to general operating conditions for Vdd and 6. SPI slave timing valuesSymbolParameterValue (1)UnitMinMaxtc(SPC)SPI clock cycle100nsfc(SPC)SPI clock frequency10 MHztsu(CS)CS setup time6nsth(CS)CS hold time8tsu(SI)SDI input setup time12th(SI)SDI input hold time15tv(SO)SDO valid output time50th(SO)SDO output hold time9tdis(SO)SDO output disable time50 1. 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

9 Figure 3. SPI slave timing diagramSPCCS SDISDOtsu(CS)tv(SO)th(SO)th(SI)tsu(SI) th(CS)tdis(SO)tc(SPC)MSB IN MSB OUT LSBOUT LSB IN Note: Measurement points are done at Vdd_IO and Vdd_IO, for both input and output interface characteristics DS11811 - Rev 6page 9 C - inter-IC control interfaceSubject to general operating conditions for Vdd and 7. I C slave timing valuesSymbolParameterI C standard mode(1)I C fast mode(1)UnitMinMaxMinMaxf(SCL)SCL clock frequency01000400kHztw(SCLL)SCL clock low stw(SCLH)SCL clock high (SDA)SDA setup time250100nsth(SDA)SDA data hold sth(ST)START condition hold stsu(SR)Repeated START condition setup (SP)STOP condition setup (SP:SR)Bus free time between STOP and START 1.

10 Data based on standard I C protocol requirement, not tested in production. Figure 4. I C slave timing diagramSDASCLtsu(SP)tw(SCLL)tsu(SDA)tsu( SR)th(ST)tw(SCLH)th(SDA)tw(SP:SR)STARTRE PEATEDSTARTSTOPSTARTNote: Measurement points are done at Vdd_IO and Vdd_IO, for both interface characteristics DS11811 - Rev 6page 10/65 Table 8. I C high-speed mode specifications at 1 MHz and MHzModeSymbolParameterMinMaxUnitFast mode plus(1)fSCLSCL clock frequency01 MHztHD;STAHold time (repeated) START condition260-nstLOWLow period of the SCL clock500-tHIGHHigh period of the SCL clock260-tSU;STAS etup time for a repeated START condition260-tHD;DATData hold time0-tSU;DATData setup time50-trDARise time of SDA signal-120tfDAFall time of SDA signal-120trCLRise time of SCL signal20* time of SCL signal20* ;STOS etup time for STOP condition260-CbCapacitive load for each bus line-550pFtVD;DATData valid time-450nstVD.