Machine Code -and- How the Assembler Works

1 Machine code -and- How the Assembler WorksMar 8 13, 20131 / 32 OutlineWhat is Machine code ?RISC vs. CISCMIPS instruction formatsAssembling basic instructionsR-type instructionsI-type instructionsJ-type instructionsMacro instructions2 / 32 Assembly language vs. Machine codeAssemblertranslates assembly code to Machine codeloop: lw $t3, 0($t0) lw $t4, 4($t0) add $t2, $t3, $t4 sw $t2, 8($t0) addi $t0, $t0, 4 addi $t1, $t1, -1 bgtz $t1, loop0x8d0b00000x8d0c00040x016c50200xad0a 00080x210800040x2129ffff0x1d20fff9 AssemblerAssembly program (text file)source codeMachine code (binary)object code3 / 32 What is Machine code ?

2 Machine code is theinterfacebetween software and hardwareThe processor is hardwired to implement Machine code the bits of a Machine instruction aredirect inputsto thecomponents of the processorThis is only true for RISC architectures!4 / 32 Decoding an instruction (RISC)5 / 32 What about CISC?Main difference between RISC and CISC RISC Machine code implemented directly by hardware CISC processor implements an even lower-levelinstruction set calledmicrocodeTranslation from Machine code to microcode is hardwired written by an architecture designer never visible at the software level6 / 32 RISC vs. CISCA dvantages of CISC an extra layer of abstraction from the hardware easy to add new instructions can change underlying hardware without changing themachine code interfaceAdvantages of RISC easier to understand and teach :-) regular structure make it easier to pipeline no Machine code to microcode translation stepNo clear winner.

3 Which is why we still have both!7 / 32 How does the Assembler assemble?loop: lw $t3, 0($t0) lw $t4, 4($t0) add $t2, $t3, $t4 sw $t2, 8($t0) addi $t0, $t0, 4 addi $t1, $t1, -1 bgtz $t1, loop0x8d0b00000x8d0c00040x016c50200xad0a 00080x210800040x2129ffff0x1d20fff9 AssemblerAssembly program (text file)source codeMachine code (binary)object code8 / 32 MIPS instruction formatsEvery assembly language instruction is translated into amachine code instruction in one of threeformats6 bits5 bits5 bits5 bits5 bits6 bitsR000000rsrtrdshamtfunctIoprsrtaddres s/immediateJoptarget address= 32 bits Register-type Immediate-type Jump-type9 / 32 Example instructions for each formatRegister-type instructions# arithmetic and logicadd $t1, $t2, $t3or $t1, $t2, $t3slt $t1, $t2, $t3# mult and divmult $t2, $t3div $t2, $t3# move from/tomfhi $t1mflo $t1# jump registerjr $raImmediate-type instructions# immediate arith and logicaddi $t1, $t2, 345ori $t1, $t2.

4 345slti $t1, $t2, 345# branch and branch-zerobeq $t2, $t3, labelbne $t2, $t3, labelbgtz $t2, label# load/storelw $t1, 345($t2)sw $t2, 345($t1)lb $t1, 345($t2)sb $t2, 345($t1)Jump-type instructions# unconditional jump # jump and linkj label jal label10 / 32 OutlineWhat is Machine code ?RISC vs. CISCMIPS instruction formatsAssembling basic instructionsR-type instructionsI-type instructionsJ-type instructionsMacro instructions11 / 32 Components of an instruction6 bits5 bits5 bits5 bits5 bits6 bitsR000000rsrtrdshamtfunctIoprsrtaddres s/immediateJoptarget addressComponentDescriptionop, functcodes that determine operation to performrs, rt, rdregister numbers for args and destinationshamt, imm, addr values embedded in the instruction12 / 32 Assembling instructionsAssemble: translate from assembly to Machine code for our purposes: translate to a hex representation of themachine codeHow to assemble a single instruction1.

5 Decide which instruction format it is (R, I, J)2. determine value of each component3. convert to binary4. convert to hexadecimal13 / 32 Determining the value of register componentsNumberNameUsagePreserved?$0$ze roconstant0x00000000N/A$1$atassembler temporaryN/A$2 $3$v0 $v1function return values7$4 $7$a0 $a3function arguments7$8 $15$t0 $t7temporaries7$16 $23$s0 $s7saved temporaries3$24 $25$t8 $t9more temporaries7$26 $27$k0 $k1reserved for OS kernelN/A$28$gpglobal pointer3$29$spstack pointer3$30$fpframe pointer3$31$rareturn addressN/A14 / 32 Components of an R-type instructionR:000000rsrtrdshamtfunctR-typ e instruction op6 bits always zero!

6 Rs5 bits 1st argument register rt5 bits 2nd argument register rd5 bits destination register shamt 5 bits used in shift instructions (for us, always 0s) funct6 bits code for the operation to perform32 bitsNote that the destination register is third in the Machine code !15 / 32 Assembling an R-type instructionadd $t1, $t2, $t3000000rsrtrdshamtfunctrs = 10 ($t2=$10)rt = 11 ($t3=$11)rd = 9 ($t1=$9)funct = 32 (look up function code foradd)shamt = 0 (not a shift instruction)0000001011903200000001010010 1101001000001000000000 0001 0100 1011 0100 1000 0010 00000x014B482016 / 32 ExercisesR:0rsrtrdshfnAssemble the following instructions: sub $s0, $s1, $s2 mult $a0, $a1 jr $raNameNumber$zero0$v0 $v12 3$a0 $a34 7$t0 $t78 15$s0 $s716 23$t8 $t924 25$sp29$ra31 Instrfnadd32sub34mult24div26jr817 / 32 Components of an I-type instructionI.

7 Oprsrtaddress/immediateI-type instruction op6 bitscode for the operation to perform rs5 bits1st argument register rt5 bitsdestination or 2nd argument register imm 16 bits constant value embedded in instruction32 bitsNote the destination register is second in the Machine code !18 / 32 Assembling an I-type instructionaddi $t4, $t5, 67oprsrtaddress/immediateop = 8 (look up op code foraddi)rs= 13 ($t5=$13)rt= 12 ($t4=$12)imm= 67 (constant value)813126700100001101011000000 0000 0100 00110010 0001 1010 1100 0000 0000 0100 00110x21AC004319 / 32 ExercisesR:0rsrtrdshfnI:oprsrtaddr/immAs semble the following instructions: or $s0, $t6, $t7 ori $t8, $t9, 0xFFNameNumber$zero0$v0 $v12 3$a0 $a34 7$t0 $t78 15$s0 $s716 23$t8 $t924 25$sp29$ra31 Instrop/fnand36andi12or37ori1320 / 32 Conditional branch instructionsbeq $t0, $t1, labelI.

8 Oprsrtaddress/immediateI-type instruction op6 bitscode for the comparison to perform rs5 bits1st argument register rt5 bits2nd argument register imm 16 bitsjump offsetembedded in instruction32 bits21 / 32 Calculating the jump offsetJump offsetNumber of instructions from thenext instruction(nopis an instruction that does nothing)beq $t0, $t1, skipnop # 0 (start here)nop # 1nop # 2skip: nop # 3!..offset = 3loop: nop # -5nop # -4nop # -3nop # -2beq $t0, $t1, loopnop # 0 (start here)offset = -522 / 32 Assembling a conditional branch instructionbeq $t0, $t1, labelnopnoplabel: nopoprsrtaddress/immediateop = 4 (look up op code forbeq)rs = 8 ($t0=$8)rt = 9 ($t1=$9)imm= 2 (jump offset)489200010001000010010000 0000 0000 00100001 0001 0000 1001 0000 0000 0000 00100x1109000223 / 32 ExercisesR:0rsrtrdshfnI:oprsrtaddr/immAs semble the following program:# Pseudocode:# do {# i++# } while (i !)

9 = j);loop: addi $s0, $s0, 1bne $s0, $s1, loopNameNumber$zero0$v0 $v12 3$a0 $a34 7$t0 $t78 15$s0 $s716 23$t8 $t924 25$sp29$ra31 Instrop/fnadd32addi8beq4bne524 / 32J-type instructionsJ:optarget addressOnly two that we care about:jandjal remember,jris an R-type instruction!Relative vs. absolute addressingBranch instructions offset is relative:PC = PC + 4 + offset 4 Jump instructions address is absolute:PC = (PC & 0xF0000000) | (address 4) Absolute relative to a 256Mb region of memory(MARS demo: )25 / 32 Determining the address of a jump0x4000000j label..0x40000A4label: nop..0x404C100j labelAddress component of jump instruction1.

10 Get address at label in hex0x40000A42. Drop the first hex digit0x 0000A4=0xA43. Convert to binary101001004. Drop the last two bits10100126 / 32 Assembling a jump instruction0x4000000j label..0x40000A4label: nop..0x404C100j labeloptarget addressop =2 (look up opcode forj)addr =101001(from previous slide)21010010000 1000 0000 0000 0000 0000 0010 10010x0800002927 / 32 Comparison of jump/branch instructionsConditional branches beq,bne offset is 16 bits effectively 18 bits, since 4 range: 218= PC 128kbUnconditional jumps j,jal address is 26 bits effectively 28 bits, since 4 range: any address in current 256Mb blockJump register jr address is 32 bits (in register) range: any addressable memory location (4GB)28 / 32 OutlineWhat is Machine code ?