Main Structural Component of a Computer System

1 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 1 Main Structural Component of a Computer System The main elements associated with a Computer System are as follows: 1. Central Processing Unit (CPU) 2. Main Memory 3. Secondary Storage Devices 4. Input and Output (I/O) Devices 5. Busses The Processor (CPU) The CPU or processor acts as the controller of all actions or services provided by the System . It is the Brain and the Heart of the Computer . The operations of a CPU can be reduced into the following : 1. Fetch the next instruction from memory. 2. Decode the instruction. 3. Execute the instruction. 4. Store the result of the instruction into main memory. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 2 In general, the CPU has three main units: (See the figure below) Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations.

2 For example, it can add together two binary numbers either from memory or from some of the CPU registers. Control Unit: controls the action of the other Computer components so that instructions are executed in the correct sequence. Registers - Temporary storage inside CPU. Registers can be read and written at high speed as they are inside the CPU. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 3 Memory The memory in a Computer System is of two fundamental types: Main Memory: used to store information for immediate access by the CPU. Main Memory is also referred to as Primary Storage or Main Store. Closely connected to the processor. The contents are quickly and easily changed. Stores the programs that the processor is actively working with. Main memory includes: Random Access memory (RAM): for temporary storage.

3 Read-only memory (ROM): for permanent storage. Secondary Storage Devices: devices provide permanent storage of large amounts of data. Secondary storage is also called: secondary memory, external memory. This storage may consist of magnetic tapes, magnetic disk, optical memory device. Connected to main memory through the bus and a controller. The contents are easily changed, but this is very slow compared main memory. Used for permanent storage of programs and data. Input/Output Devices Input/output devices provide an interface between the Computer and the user. There is at least one input device ( keyboard, mouse, measuring device such as a temperature sensor) and at least one output device ( printer, screen, control device such as an actuator). Input and output devices like keyboards and printers, together with the external storage devices, are referred to as peripherals.

4 System Bus There are three types of busses: 1. Address Buss: A unidirectional lines determine the size of memory addressable by the processor. 2. Data Bus : A bi-directional lines indicate the size of the data transferred between the processor and memory or I/O device. 3. Control Bus: consists of a set of control signals indicates the type of action taking place on the System bus. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 4 Evolution of Intel Microprocessor Intel (Integrate electronics) was the first corporation in manufacturing Microprocessors starting with 4004 P to Pentium P. Processor vary in their speed, capacity of memory, register width, and address & data bus size, a brief description of various Intel processor is explained in the table below. P Size of Data Bus Size of Address Bus Register Width (bit) Memory Size Clock Rate 4004 4 12 4 4 Kbyte MHz 8008 8 14 8 16 Kbyte MHz 8080 8 16 8 64 Kbyte 2 MHz 8085 8 16 8 64 Kbyte 3 MHz 8086 16 20 16 1 Mbyte 5 MHz 8088 8 20 16 1 Mbyte 5 MHz (4004-8085)

5 8086 P integer numbers P 0808 floating numbers 86180 16 28 16 1 Mbyte 6 MHz 80286 16 24 16 16 Mbyte 8 MHz P 08208 floating numbers 80386 32 32 32 4 Gbyte 16 MHz P 08308 floating numbers 80486 32 32 32 4 Gbyte + 8 Kbyte cache 50 MHz P 08408 floating numbers Pentium 64 32 32 4 Gbyte + 8 Kbyte cache 100 MHz Pentium Pro 64 36 32 64 Gbyte + 8K L1 cache +256K L2 cache 180M Hz Pentium II 64 36 32 64 Gbyte + 32K L1 cache +512K L2 cache 233 - 450 MHz Pentium III 64 36 32 64 Gbyte + 32K L1 cache +512K L2 cache 1 GHz Pentium IV 64 36 32 64 Gbyte + 32K L1 cache +512K L2 cache GHz 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A.

6 H. ALDOURI 5 Intel's 8086 Microprocessor The 8086 P is manufactured using High performance Metal-Oxide Semiconductor (HMOS) technology. It has approximately 29000 transistors and housed in a 40-pin package. Internal Architecture of 8086 P The architecture of 8086 P is shown in figure below . It has two separate functional units : Bus Interface Unit (BIU) and Execution Unit (EU). The 8086 P architecture employs parallel processing , both the units (BIU and EU) work at the same time. Parallel processing makes the fetch and execution of instructions independent operations. This results in efficient use of the System bus and higher performance for 8086 P systems. The BIU has segment registers, instruction pointer, address generation and bus control logic block, instruction queue. The main jobs performed by BIU are: 1. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands.

7 2. Input/output of data from/to input/output peripherals. The EU has general purpose registers, ALU, control unit, instruction register, flags (or status) register. The main jobs performed by the execution unit EU are: 1. Decoding/execution of instructions. 2. It accepts instructions from the instruction queue and data from the general purpose registers or memory. 3. EU tests the status of flags in the control register and updates them when executing instructions. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 6 Pipelining is a process that allows the CPU (Microprocessor) to fetch and execute instructions at the same time. Intel Co. implemented the concept of pipelining by splitting the internal architecture of the 8088/8086 P into two units that works simultaneously: Q: Explain the operations of instructions queue in BIU.

8 Ans. The instruction queue is 6- bytes in length, operates on FIFO (first-in first-out) basis. It receives the instruction codes from memory. BIU fetches the instructions for the instructions queue from memory. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 8 Types of Buses in the 8086 P A bus is a number of wires organized to provide a means of communication among different elements in a microcomputer System . There are three types of buses: 1. Address Bus : A 20-bit unidirectional lines used hold the address of a memory location. The address bus allows the processor to access 1 Mbyte of memory (Memory size = 220 =1048576 bytes = 1 Mbyte). 2. Data Bus : A 16-bit bidirectional lines used for transferring data between the microprocessor and memory or the peripheral devices. 3. Control Bus : It contains lines that select the memory or I/O and cause them to perform a read or write operation.

9 Internal Registers of 8086 P There are fourteen 16-bit registers. The different groups are: The data group (general purpose registers) consists of AX (accumulator), BX (base), CX (count) and DX (data). Pointer group consists of SP (Stack pointer), BP (Base pointer), IP (Instruction pointer). Index group consists of SI (Source Index), and DI (Destination index). Segment group consists of CS (Code Segment), DS (Data Segment) , SS(Stack Segment) and ES (Extra Segment),. 16-bit flags (status) register. Figure below shows the registers placed in the different groups. 8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI 0 General Purpose Data Registers Figure below shows the four data registers with their dedicated functions. Pointers and Index Group The pointer registers are SP (Stack Pointer), BP (Base pointer) and IP (Instruction Pointer) while the index registers are SI (Source Index) and DI (Destination Index).

10 All the five are 16-bit registers and are used to store offset (effective address) of memory locations relative to segment registers. Segment Registers : there are four segment registers, they are: 1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored. 2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address. 3. Stack Segment (SS): SS defines the area of memory used for the stack. 4. Extra Segment (ES): ES is additional data segment that is used by some of the string instructions to hold the destination data. 15 8 7 0