MCP3913 Data Sheet - Microchip Technology

1 MCP3913 . 3V Six-Channel Analog Front End Features: Description: Six Synchronous Sampling 24-bit Resolution The MCP3913 is a 3V six-channel Analog Front End Delta-Sigma A/D Converters (AFE), containing six synchronous sampling delta- dB SINAD, -107 dBc Total Harmonic sigma, Analog-to-Digital Converters (ADC), six PGAs, Distortion (THD) (up to 35th Harmonic), 112 dBFS phase delay compensation block, low-drift internal SFDR for Each Channel voltage reference, digital offset and gain error calibration registers, and high-speed 20 MHz Enables Typical Active Power Measurement SPI-compatible serial interface. Error over a 10,000:1 Dynamic Range The MCP3913 ADCs are fully configurable, with Advanced Security Features: features such as: 16/24-bit resolution, Oversampling - 16-bit Cyclic Redundancy Check (CRC) Ratio (OSR) from 32 to 4096, gain from 1x to 32x, Checksum on All Communications for Secure independent Shutdown and Reset, dithering and auto- Data Transfers zeroing.

2 The communication is largely simplified with 8- - 16-bit CRC Checksum and Interrupt Alert for bit commands, including various continuous read/write Register Map Configuration modes and 16/24/32-bit data formats that can be - Register Map lock with 8-bit Secure Key accessed by the Direct Memory Access (DMA) of an AVDD, DVDD 8/16- or 32-bit MCU, and with the separate data ready pin that can directly be connected to an Interrupt Programmable Data Rate up to 125 ksps: Request (IRQ) input of an MCU. - 4 MHz Maximum Sampling Frequency The MCP3913 includes advanced security features to - 16 MHz Maximum Master Clock secure the communications and the configuration Oversampling Ratio up to 4096 settings, such as a CRC-16 checksum on both serial Ultra-Low Power Shutdown Mode with < 10 A data outputs and static register map configuration.

3 It -122 dB Crosstalk between Channels also includes a register-map lock through an 8-bit Low Drift Internal Voltage Reference: secure key to stop unwanted write commands from 9 ppm/ C processing. Differential Voltage Reference Input Pins The MCP3913 is capable of interfacing with a variety of voltage and current sensors, including shunts, current High Gain PGA on Each Channel (up to 32 V/V). transformers, Rogowski coils and Hall-effect sensors. Phase Delay Compensation with 1 s Time Resolution Applications: Separate Data Ready Pin for Easy Synchronization Polyphase Energy Meters Individual 24-bit Digital Offset and Gain Error Energy Metering and Power Measurement Correction for Each Channel Automotive High-Speed 20 MHz SPI Interface with Mode 0,0 Portable Instrumentation and 1,1 Compatibility Medical and Power Monitoring Continuous Read/Write Modes for Minimum Audio/Voice Recognition Communication Time with Dedicated 16/32-bit Modes Available in a 40-lead UQFN and 28-lead SSOP.

4 Packages Extended Temperature Range: -40 C to +125 C. 2013 Microchip Technology Inc. DS20005227A-page 1. MCP3913 . Package Type MCP3913 MCP3913 . RESET. CH0+. DVDD. CH1+. DGND. AGND. AVDD. SSOP 5x5 UQFN*. CH0- CH1- NC. AVDD 1 28 DVDD 40 39 38 37 36 35 34 33 32 31. CH0+ 2 27 RESET. CH2+ 1 30 SDI. CH0- 3 26 SDI 29 SDO. CH2- 2. CH1- 4 25 SDO 28 SCK. CH3- 3. CH1+ 5 24 SCK 27 CS. CH3+ 4. CH2+ 6 23 CS EP 26 OSC2. NC 5. CH2- 7 22 OSC2 41. 25 OSC1/CLKI. CH3- 8 21 OSC1/CLKI NC 6. CH4+ 7 24 DGND. CH3+ 9 20 DGND. CH4+ NC CH4- 8 23 NC. 10 19. CH4- 11 18 DR CH5- 9 22 DR. CH5- DGND CH5+ 10 21 DGND. 12 17. CH5+ 13 16 AGND 11 12 13 14 15 16 17 18 19 20. REFIN- REFIN+/. OUT. NC. NC. NC. NC. AGND. AVDD. NC. DVDD. REFIN+/OUT 14 15 REFIN- * Includes Exposed Thermal Pad (EP); see Table 3-1.

5 Functional Block Diagram AVDD DVDD. REFIN+/OUT. Voltage VREFEXT AMCLK Xtal Oscillator Reference OSC1. MCLK. + Clock Vref DMCLK/DRCLK. Generation OSC2. REFIN- - Vref- Vref+. DMCLK OSR<2:0>. OSR/2- OFFCAL_CH0 GAINCAL_CH0 PRE<1:0>. PHASE1 <11:0> <23:0> <23:0>. CH0+ +. CH0- - MOD<3:0> ) + X DATA_CH0<23:0>. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. OFFCAL_CH1 GAINCAL_CH1. OSR/2 <23:0> <23:0>. CH1+ +. CH1- - MOD<7:4> ) + X DATA_CH1<23:0>. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. OSR/2- OFFCAL_CH2 GAINCAL_CH2. PHASE1 <23:12> <23:0> <23:0>. CH2+ +. CH2- - MOD<11:8> ) + X DATA_CH2<23:0>. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. OFFCAL_CH3 GAINCAL_CH3. Digital SPI. OSR/2 <23:0> <23:0> Interface CH3+ +.

6 CH3- - MOD<15:12> ) + X DATA_CH3<23:0>. DR. SDO. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. RESET. OSR/2- OFFCAL_CH4 GAINCAL_CH4 SDI. PHASE0<11:0> <23:0> <23:0>. CH4+ SCK. +. CH4- - MOD<19:16> ) + X DATA_CH4<23:0>. CS. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. OFFCAL_CH5 GAINCAL_CH5. OSR/2 <23:0> <23:0>. CH5+ +. CH5- - MOD<23:20> ) + X DATA_CH5<23:0>. PGA ' 6 Phase SINC3+ Offset Gain Modulator Shifter SINC1 Cal. Cal. POR POR. AVDD DVDD. Monitoring Monitoring ANALOG DIGITAL. AGND DGND. DS20005227A-page 2 2013 Microchip Technology Inc. MCP3913 . ELECTRICAL Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to CHARACTERISTICS. the device. This is a stress rating only and functional operation of the device at those or any other condi- Absolute Maximum Ratings tions, above those indicated in the operational listings VDD.

7 To of this specification, is not implied. Exposure to maxi- Digital inputs and outputs AGND .. to mum rating conditions for extended periods may affect Analog input AGND ..-2V to +2V device reliability. VREF input AGND .. to VDD + Storage temperature ..-65 C to +150 C. Ambient temp. with power applied ..-65 C to +125 C. Soldering temperature of leads (10 seconds) .. +300 C. ESD on the analog inputs (HBM,MM) .. kV, 300V. ESD on all other pins (HBM,MM) ..2 kV, 300V. Electrical Specifications TABLE 1-1: ANALOG SPECIFICATIONS. Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz;. PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, VCM = 0V;. TA = -40 C to +125 C;VIN = dBFS @ 50/60 Hz on all channels.

8 Characteristic Sym. Min. Typ. Max. Units Conditions ADC Performance Resolution 24 bits OSR = 256 or greater (No missing codes). Sampling Frequency fS(DMCLK) 1 4 MHz For maximum condition, BOOST<1:0> = 11. Output Data Rate fD(DRCLK) 4 125 ksps For maximum condition, BOOST<1:0> = 11, OSR = 32. Analog Input Absolute CHn+/- -1 +1 V All analog input channels, Voltage on CHn+/- pins, measured to AGND. n between 0 and 5. Analog Input IIN +/-1 nA RESET<5:0> = 111111, Leakage Current MCLK running continuously Differential Input (CHn+-CHn-) -600/GAIN +600/GAIN mV VREF = , Voltage Range proportional to VREF. Offset Error VOS -1 1 mV Note 5. Offset Error Drift V/ C. Gain Error GE -4 +4 % Note 5. Gain Error Drift 1 ppm/ C. Note 1: Dynamic Performance specified at dB below the maximum differential input value, VIN = VPP = 424 mVRMS @ 50/60 Hz, VREF = See Section Terminology And Formulas for definition.

9 This parameter is established by characterization and not 100% tested. 2: For these operating currents, the following configuration bit settings apply: SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000, VREFEXT = 0, CLKEXT = 0. 3: For these operating currents, the following configuration bit settings apply: SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1. 4: Measured on one channel versus all others channels. The average of crosstalk performance over all channels (see Figure 2-32 for individual channel performance). 5: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical performance. 6: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to the part with no damage.

10 7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. 2013 Microchip Technology Inc. DS20005227A-page 3. MCP3913 . TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED). Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz;. PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, VCM = 0V;. TA = -40 C to +125 C;VIN = dBFS @ 50/60 Hz on all channels. Characteristic Sym. Min. Typ. Max. Units Conditions Integral Non-Linearity INL 5 ppm Measurement Error ME % Measured with a 10,000:1.