MEMS Solution for Semiconductor Probing - SWTest.org

1 mems Solution for Semiconductor ProbingMEMS Solution for Semiconductor ProbingSouthSouth--Western Testing Workshop PresentationWestern Testing Workshop Presentation SCS Hightech by Dr. Howard Hsu06-06-200522 Presentation OverviewMEMS Probing Technology Roadmap- Compliant Probing Structure- Tighter Control of Electrical ConnectionIntroduction- Device Geometry vs. IC Characteristics- Device Geometry vs. Pad Layout Rule and Package Technology- Classical Probing Technology is Insufficient at These Circumstances- Mechanical Probing Has Shown Productivity Degradation in Volume Production- mems VPC SolutionProbing Mechanism Comparison Classical vs.

2 mems - Structural Differences- Material Combination & Technology Development- Mechanism Practices- Performance ComparisonDevelopment Challenges & solutions for mems Probing - Test, Assembly, and Operation - Reliability - IC Concerns mems Solution for Semiconductor ProbingMEMS Solution for Semiconductor ProbingIntroductionIntroduction44 IntroductionDevice Geometry vs. IC CharacteristicsKGDKGDW afer Level burn InWafer Level burn InI/O pins over 1000I/O pins over 1000 High speed testHigh speed testBurnBurn--in and test before packagein and test before packageVertical Probe CardVertical Probe CardTestingTesting PbPb--Free Solder BumpFree Solder BumpUnferfill Development Unferfill Development Materials, Reliability, MCMM aterials, Reliability, MCMCOBCOBBBULBBULFlip Chip PackageFlip Chip PackagePackagePackage Number of transistors Number of transistors Increase Increase Speed greater than 300 MHzSpeed greater than 300 MHzNumber of function, I/O, power, and Vdd & Vss are Number of function, I/O, power.

3 And Vdd & Vss are faster than 300 MHz, package no wire faster than 300 MHz, package no wire of I/Os increases too fast, therefore Array Number of I/Os increases too fast, therefore Array Design is the major is the major Power Increase Increase ComponentsComponents Smaller transistor, large quantity, faster transistor, large quantity, faster / Photo down to Stepper / Photo down to umumLow leakage, capacitor effects, thermal conductivity, Low leakage, capacitor effects, thermal conductivity, power consumption, and higher integration consumption, and higher integration k Low k dielectric ~ ~ power consume & voltage, Energy storageLow power consume & voltage, Energy storageSOI CapacitorSOI CapacitorLow Resistance & Electronic migrationLow Resistance & Electronic migrationHigh conductivity & Thermal ConductivityHigh conductivity & Thermal ConductivityCopper ProcessCopper ProcessProcess Process TechnologyTechnology Remarks Remarks 20032003--2005200555 IntroductionDevice Geometry vs.

4 Pad Layout Rule and Package TechnologyDevice Technology is going Pad Layout Rule is getting more and more Technology has to be changed in order to fit the chip packageWire Bonding PackagePad Pitch over 200umPad Pitch over 200umPad Pitch under 100umAbove ~ ~ ~ ~ ~ below2004~Linear Bump DesignStagger Bump DesignArray Bump Design66 IntroductionClassical Probing Technology is Insufficient at These Circumstances Array Bump Probing - Bump pitch will need to go lower than 150um- Maintenance free probe card- No burning tips- Short lead-time for order delivery- Consistent Probing ; no need to re-probe- High frequency Probing Aluminum Pad Probing - Multiple sites- Small pad pitch ~ 50um77 Results huge customer service efforts!

5 !!IntroductionMechanical Probing Has Shown Productivity Degradation in Volume Production Long repair timeBurning TipsPad ScratchLow Probing lifeResults a higher cost and lower efficiency!!!Long offline cleaningLow productivityHigher noiseExpensive rework88 IntroductionMEMS VPC Solution mems Prove Card SpecificationsMEMS Prove Card Specifications2 ohm whole path2 ohm whole pathPath ResistancePath ResistanceNickel, Copper, and SilverNickel, Copper, and SilverMajor MaterialMajor MaterialSmaller than 10nA at 5 voltsSmaller than 10nA at 5 voltsLeakageLeakage50 ohm plus minus 5 ohm50 ohm plus minus 5 ohmImpendence MatchImpendence Match< 2 weeks< 2 weeksRepeat order LTRepeat order LT6~8 weeks (design related)6~8 weeks (design related)11ststorder Leadorder Lead--timetime100g / pin100g / pinShear ForceShear Force1 A1 AMax.

6 CurrentMax. Current< < Accuracy 120um array, 35um LDI120um array, 35um LDIMin. Probing PitchMin. Probing Pitch0 ~ 4 inch0 ~ 4 inchMax. Probing AreaMax. Probing AreaUp to 100umUp to 100umProbe Tip HeightProbe Tip Height8 ~ 12 um8 ~ 12 umProbe Tip Probe Tip DimensionDimensionVertical Probe card for Aglient 93000 Vertical Probe Card for Cadence TypeHere is the Solution !! mems Solution for Semiconductor ProbingMEMS Solution for Semiconductor ProbingProbing Mechanism Comparison Probing Mechanism Comparison Classical vs. MEMSC lassical vs. MEMS1010 Probing Mechanism Comparison Classical vs. MEMSS tructure DifferencesClassical Vertical Type Probe Card- Probing tip will deform cause open issue- Use PCB substrate- Need cleaning both online and offlineMEMS Vertical Type Probe Card- Rigid tip will never deform- Use ceramic substrate- Excellent co-planarity w/o manual adjustment- No cleaning, no re- Probing , and no repairing1111 Probing Mechanism Comparison Classical vs.

7 MEMSM aterial Combination Automated LayoutNickel TipCopperContact PadsCopper RDLLTCC SubstrateInter-relation of all process parameters: Chemicals, Temp., Plasma, double side etcCeramic Substrate RDLVia AreaTipContact PadsMaterial content of each part1212 Probing Mechanism Comparison Classical vs. MEMST echnology Development10um50umClassical VPC:Use the mechanical technology minimum pitch is ~150um for array VPCMEMS VPC: Use the same process to fabricate the sub-micron level rigid be applied to small pitch ~35um multiple die Mechanism Comparison Classical vs. MEMST echnology DevelopmentUse the same process technology to fabricate the sub-micron level rigid tips for LCD driver IC 45um pitch rigid tip of dual-site LCD Driver IC probe card photo under Mechanism Comparison Classical vs.

8 MEMSM echanism Before ProbingAfter ProbingClassical Vertical ProbingMEMS Vertical ProbingPressed bumpResiduesTip slopingDimpleNo residueTip no changeAlignment is correctAlignment is NOTcorrect1515 Probing Mechanism Comparison Classical vs. MEMSP erformance 2 weeks2 weeks4 weeks4 weeksVolume lead timeVolume lead timeRepeat orderRepeat orderTip cleaningTip cleaningReprobingReprobingLDI probingLDI probingMultiple Site Multiple Site ProbingProbingVolume lead timeVolume lead timeFirst orderFirst orderPad PitchPad PitchBumped pad only Bumped pad only for nowfor nowDepends on pad pitchDepends on pad pitch5 ~ 6 weeks5 ~ 6 weeks6 ~ 8 weeks6 ~ 8 weeksUnder 120 umUnder 120 um> 150 um> 150 umNo need, nor online maintenanceNo need, nor online maintenanceNeed, because residueNeed, because residueNo needNo needNeedNeedAlready in evaluation sampleAlready in evaluation sampleNot available (other types.)

9 Not available (other types, such as cantilever)such as cantilever)SCS Diamond Vespa SCS Diamond Vespa mems VPCMEMS VPCC lassical C type Probe CardClassical C type Probe CardComparison Table for different probe card1616 Probing Mechanism Comparison Classical vs. MEMSP erformance (MHz)Level (V)Step 1 Step 2 Step 3C typeSCST ester internal signal qualityMEMS Vertical Probe Card Has passed several qualifications in Taiwan. Electrical performance (up to 3 GHz) is superior to classical manufactured probe cards. mems Solution for Semiconductor ProbingMEMS Solution for Semiconductor ProbingDevelopment Challenges & solutions For mems ProbingDevelopment Challenges & solutions For mems Probing1818 Probing PressureAbout ~25g per tip with our tip head shapeLong neck cone shape for non-uniformity of the focus issues tip head is 10umSOP training for using mems probe BoardParallelism between PCB and LTCCR equires high Challenges & solutions For mems ProbingTest, Assembly, and OperationChuckLoad BoardTester Head UnitTesterSolder BumpWafer1919 Durabilityfor Probing ICsExcellent Probing consistency (eliminate re- Probing )

10 Excellent Probing life time some model probed over , other around maintenance No need to repair anymore because lead time is 150K timesAfter 350K timesResult:- With clean process, the wear out rate is around 3~6 um after 12k times. - Probe without clean process, there is almost no wear out (pin-height) after 350k insertions. Subject: SCS mems VPC for 8 wafers(633 pins)Tester/Prober: Agilent 93000/P600, P12/TELC lean sheet: Enhanced 3M type C (type C + polish paper/pink type)Tool: Olympus microscope with micro meterReading: Check pin high twice( from ULTCC to tip) for Challenges & solutions For mems ProbingReliability2020 Rigid TipAfter the tip probes into the bump.