MIPI D-PHY Interface Test

1 MIPI D-PHY Interface TestJack LeeAgenda MIPI D-PHY Overview Test Solutions with Standard Digital D-PHY Rx D-PHY Tx Improved Testing Capability FPGA Solution on DIB Protocol Aware (PA) Hardware Source-SynchronousMIPI D-PHY IP CoreOverviewMIPI D-PHY is a High-speed low power serial transceiver Interface supporting interconnections of a wide range of low-power high-speed mobile applications such as digital Camera Serial Interface (CSI), graphic Display Serial Interface (DSI), UniPro and other MIPI devices using the PHY Protocol Interface (PPI). Flexible Low cost High Speed Low power consumption Serial interfaceMIPI UniPro CSI-2 RXTXDSI DigRFv4(M-PHY) orD-PHY for WiMAXMIPI D-PHY Full Block Diagram(LP-Contention Detector)Universal Lane Mode ArchitectureSupport DSIMIPI D-PHY Block Diagram for TX and RXSupport CSIB lock Diagram for TransmitterBlock Diagram for ReceiverMIPI D-PHY Characteristics Data lanes High-Speed ModeLevel: 400mVpp, differential for 100 ohm terminationSpeed: 80Mb/s -1Gb/sSynchronous transfer Low-Power Mode Level: CMOS level driver, single-endedSpeed.

2 < 10 MbpsLane 0 only has LP signalAsynchronous transfer Bi-directionality (HSx ) Lane scalability N data lanes + 1 Clock Lane Interconnect PCBs, flexfoils, cables, connectors Low pin and wire count Power Low operational power (mW-range) Very low stand-by power (uW-range) Robustness Low EMI Ease of integration Noisy environmentTolerance ~10mVdiff ~100mVcomMIPI D-PHY Interface Overview1. Serial High-speed: Fully-terminated differential signaling First generation: Source-Synchronous with/without encoding2. Low-Power: unterminated CMOS-like signalingHF filtering and CMOS-like signalingHF filtering and hysteresis for noise immunity3. Contention detection for Bi-directionalityOptional reverse data transfers are Master synchronousMIPI D-PHY Timing and level SpecificationHigh speed transmission in burstLine LevelSignal Directions & Protocol ImplementationsMODED evice (Baseband Processor)HS DrvHS RcvLP DrvLP RcvTesterHS RcvHS DrvLP RcvLP DrvDiffDiffSESETermTermHiZHiZD-PHY Rx-YYYCSI-2-YY/NY/ND-PHY TxY-YYDSIY-YYNote: LP signaling only used on Lane0 CSI, DSI do not support reverse traffic in the HS/4 rateAgenda MIPI D-PHY Overview Test Solutions with Standard Digital D-PHY Rx D-PHY Tx Improved Testing Capability UP1100 Protocol Aware (PA) Hardware Source-SynchronousD-PHY Rx (CSI) RequirementsDevice modes.

3 Receive HS mode differentially Receive LP mode single-ended (unterminated) Drive LP mode single-endedTest ConditionsUltraFLEX OptionsTest SolutionD-PHY Modes (per-Burst)DIB Components# chans per DIFF Pair# of unique levels(per-line)LP TerminationCSI-2D-PHY Rx Device receives HSUP800 HSD1000UP1100 None23 drive- Device receives HS Device receives LP Device drives LPUP800 HSD1000UP1100 None23 drive2 compare50 to resistors per line44 drive2 compareHiZTester Requirements: Drive 3(/4) levels per-line Drive Differential & Single-Ended 2 compare levels per-line Unterminated compare**Requires that the LP/HS mode switching is deterministic in both order& timeUP800 2 digital channels per diff pair 3 unique levels from tester drive Tester receive of LP only in terminated mode 50ohm term to Vt = LP_Vih = Device must handle driving LP into 50ohms to RX50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo 50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo DIFFCmp_Hi_diffCmp_Lo_diffActive load not shownParamProgrammedUseVil0 VHS/LP VloVih100mV-300mVHS VhiPE ModeLargeSwing-VT-MODED eviceHS DrvHS RcvLP DrvLP RcvTesterHS RcvHS DrvLP RcvLP DrvD-PHY Rx-YYYCSI-2-YY/NY/NCH1CH0 LPHS.

4 LP** due to scope 50 ohm terminationVilVihVt-50ohm-termLP-0 Capture LP-1 CaptureLP-0 DrvHS + Drv LP-1 DrvHS -Drv TerminatedTerminatedXD-PHY RxOption #1: 3-Level Drive, Terminated LP 4 digital channels per diff pair 3 unique levels from tester drive Allows tester to HiZ for LP receive LP receive with all channels HiZ will affect signal integrity OK since LP is such low speed (<10 Mhz) Resistor network only required on Lane0 which supports LP trafficMODED eviceHS DrvHS RcvLP DrvLP RcvTesterHS RcvHS DrvLP RcvLP DrvD-PHY Rx-YYYCSI-2-YY/NY/N50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo 50 Drv_HiDrv_LoDrv_termCmp_HiCmp_LoDIFFCmp_ Hi_diffCmp_Lo_diffVihVilVt50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo 50 Drv_HiDrv_LoDrv_termCmp_HiCmp_LoDIFFCmp_ Hi_diffCmp_Lo_diffVihVilVtDUTD-PHY RXActive load not shown8 100 8 8 100 8 CH1CH0CH3CH2 LPHS, LP** due to scope 50 ohm terminationLP-0 Cap LP-1 Cap LP-0 Drv HS+ XXXXHS Drv 50 Ohm onLP Capture -HizParamProgrammedUseChan 0, 1 (HS)VilVcm -2*Vdiff/2HS VilVihVcm + 2*Vdiff/2HS VihVt--PE ModeLargeSwing-HiZ-ParamProgrammedUseCha n 2, 3 (LS)

5 Vil0 VLP VihVt--Vol550mVLP VolVoh680mVLP VohPE ModeLargeSwing-HiZD-PHY RxOption #2: 3-Level Drive, Unterminated LPD-PHY Tx (DSI) RequirementsDevice modes: Drives HS differential Drives LP single-ended Receive LP single-ended (unterminated)Tester Requirements (within a single burst): Compare differential & single-ended Terminated & Unterminated compare 4 compare levels (per-line) 3 bits of unique compare data (per-pair) Drive 2 levels per-lineTest ConditionsUltraFLEX OptionsTest SolutionD-PHY Modes (per-Burst)DIB Components# chans per DIFF Pair# of unique levelsLP TerminationDSID-PHY Tx Device drives HSUP800 HSD1000UP1100 None22 compare per burst- Device drives HS Device drives LP Device receives LPUP800 HSD1000UP11003 resistors per line44 compare2 driveHiZ**Requires that the LP/HS mode switching is deterministic in both order& time 4 digital channels per diff pair Use 2 Time Sets; one for LP compare and one for HS compare 1.

6 (HS) that allows Drv-Term on all chans PE stays in previous state; 50 to either at Vil or Vih 2. (LP) does NOT allow Drv-Term on all chans LP receive with all channels HiZ will affect signal integrity Expect ok as LP is low speed HS receive is doubly terminated to some level Use DIFF comparator Resistor network only required on Lane0 which supports LP trafficParamProgrammedUseChan 0,1 (HS)VilHS VtVihHS VtVt--VolHS VolVohHS VohPE ModeLargeSwing-HiZ-Chan 2,3 (LP)Vil0 VLP VihVt--Vol550mVLP VolVoh880mVLP VohPE ModeLargeSwing-HiZ-MODED eviceHS DrvHS RcvLP DrvLP RcvTesterHS RcvHS DrvLP RcvLP DrvD-PHY TxY-YYDSIY-YY50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo 50 Drv_HiDrv_LoDrv_termCmp_HiCmp_LoDIFFCmp_ Hi_diffCmp_Lo_diffVihVilVt50 VihVilVtDrv_HiDrv_LoDrv_termCmp_HiCmp_Lo 50 Drv_HiDrv_LoDrv_termCmp_HiCmp_LoDIFFCmp_ Hi_diffCmp_Lo_diffVihVilVtDUTD-PHY TXActive load not shown8 100 8 8 100 8 CH1CH0CH3CH2HS, LPLPHS+ Cap HS-Cap HS Cap-diff LP-0 Cap LP-1 Cap LP-0 Drv LP-1 Drv XXXHS Drv 50 Ohm onLP Capture -HizD-PHY TxHS modified Vt/Vcomp, LP HiZAgenda MIPI D-PHY Overview Test Solutions with Standard Digital D-PHY Rx D-PHY Tx Improved Testing Capability UP1100 Protocol Aware (PA)

7 Hardware Source-Synchronous In mission-mode HS packets are separated by LP commandsHS packet lengths varyStandard Digital (no PA)*Mode switches between HS/LP modes must be deterministic in: Order Time*Packet lengths must be deterministicLgP StructureState Transitions & Non-Determinism PA in UP1100 could automatically handle the timing non-determinism The orderof packets and HS/LP transitions must still be deterministic Less DFT required More coverage testing near mission-modeTTTimingPin ElectronicsPEHostComputerFPGA BasedProtocol EnginesDUT stored response digitalDSSCL ogicPatgenTransactionMemoryHandling Non-DeterminismWith UP1100 PAUP1100 has hardware source-sync capability behind the digital pins 4 of Each 16 pin block have source sync capability Each Source Sync Input can be SE or Differential Each Source Sync Input has local adjust capability for fast edge searches Data Channels use internal Strobe or Source Sync Strobe Src Sync Clock to

8 Data pin Accuracy +/100psHS CLKHS Data 0HS Data 1HS Data 2HS Data 3 TimingLogicPADeviceD-PHYTxUP1100** Real-time AC parametric measurements: 1 burst for accurate timing measurement compared to many burst iterations for software-based solutions** Supports both PA and standard logic testingSource-Sync Timing Measurement of Device HS TxWith UP1100 PAConclusions D-PHY mode switching within a burst creates unique test challenges UltraFLEX digital solutions solve these challenges with flexible timing and pin electronics UP1100 Option adds unique capability to improve test coverage More mission-mode testing allowed by PA handling non-determinism Hardware Source-Synchronous feature allows real-time AC parametric timing measurementsAppendix A LP signal timing parameters-1 Appendix B LP signal timing parameters-2 Appendix C D-PHY Signal LevelAppendix D HS Transmitter DC SpecificationsAppendix E HS

9 Transmitter AC SpecificationsAppendix F LP Transmitter DC SpecificationsAppendix G LP Transmitter AC SpecificationsAppendix H HS Receiver DC SpecificationsAppendix I HS Receiver AC SpecificationsAppendix J LP Receiver DC and AC SpecificationsAppendix K LP Transmitter AC SpecificationsMIPI D-PHY Interface Source and Capture Voltage LevelsAppendix L