Op Amp Precision Design: DC Errors - Microchip Technology

1 AN1177. op amp Precision design : DC Errors Author: Kumen Blake DC SPECIFICATIONS. Microchip Technology Inc. There are a small number of DC specifications that describe Errors at the input of an op amp . This section INTRODUCTION organizes these specifications into those related to the input offset and the others related to input bias Engineers that use op amps in their circuits; especially currents. those new to analog or op amp circuit design . Also intended for engineers that want to understand op amp Ideal op amp DC specifications. Figure 1 shows the ideal, DC model for op amps (the Description external circuitry is not shown). All error sources are ignored and the open-loop gain (AOL) is infinite. The This application note covers the essential background output voltage is related to the input voltages as shown information and design theory needed to design a in Equation 1. Precision DC circuit using op amps. Topics include: op amp DC Specifications VN.

2 Circuit Analysis VOUT. Circuit Optimization AOL. VI. Advanced Topics References FIGURE 1: Ideal, DC op amp Model. This application note is limited to voltage feedback (traditional) op amps. Those interested in current feed- EQUATION 1: back op amps will benefit from the information here; the DC specifications and op amp DC model have many V OUT = A OL ( V N V I ). similarities. For those that are interested, a simple circuit for When negative feedback is applied, the ideal op amp 's measuring input offset voltage has been included in infinite gain forces VN and VI to be exactly equal; this is Appendix A: Input Offset Measurement Circuit . the virtual short that some authors talk about. [ 1, 2]. When positive feedback is applied ( , when used as a comparator), VOUT swings as far negative or positive as it can (to the rails), depending on the sign of the dif- ference (VN VI). op amp Model with DC Errors Figure 2 shows a physically based, DC model for op amps.

3 VPLUS and VMINUS are the external input volt- ages, while VN and VI are the internal input voltages. VOST represents the total input offset voltage error. The non-inverting bias current (IBN) and inverting bias cur- rent (IBI) represent the physical currents seen at each of the two input pins. AOL is the finite DC open-loop gain. 2008 Microchip Technology Inc. DS01177A-page 1. AN1177. It is important to understand the units for these VDD specifications. An engineer not used to op amp data sheets may be confused by the units shown. The following list should clear up the confusion. VOST. VN VOS units are: mV or V. VPLUS AOL units do not usually report the relationship VOUT. VMINUS AOL shown above: VI. - V/V for 1/AOL = VOST/ VOUT. - dB for 20log(AOL). IBN IBI CMRR units are similar to the AOL units: - V/V for 1/CMRR = VOST/ VCM. - dB for 20log(CMRR). VSS. PSRR units are similar to the AOL units: FIGURE 2: Physically Biased, DC Op - V/V for 1/PSRR = VOST/ (VDD VSS).

4 Amp Model. - dB for 20log(PSRR). Input Offset Related Specifications VOS/ TA units are: V/ C or nV/ C. A positive VOST creates a positive shift in the output Note: Notice that the gains AOL, CMRR and voltage (VOUT). The DC voltages are: PSRR, when reported in V/V, are actually their reciprocals. This form of the gains is EQUATION 2: best for statistical analyses; the values tend to have a Gaussian distribution. V N = V PLUS + V OST. V I = V MINUS Sometimes PSRR is split in two pieces: PSRR+ that is related to changes in VDD ( VDD) and PSRR that is V OUT = A OL ( V N V I ). related to changes in VSS ( VSS). = A OL ( ( V PLUS V MINUS ) + V OST ). These quantities are lumped together in the following equation, where the changes in bias voltages are from The total input offset voltage (VOST) collects the those specified for VOS (all units are converted to either following specifications into one, easy to use V or V/V): parameter: Input Offset Voltage (VOS): EQUATION 3: - Specified offset V OUT V CM V.

5 DD V SS V OS. - Describes VOST at a specific bias point V OST = V OS + -------------------- + ----------------- + ----------------- + --------------- + T A ---------------- A. OL. CMRR PSRR PSRR TA. DC Open-Loop Gain (AOL): - AOL = VOUT/ VOST Notice that all of the specifications will give a positive Common Mode Rejection Ratio (CMRR): change in VOST when the corresponding changes are positive. - CMRR = VCM/ VOST. - VCM is the common mode input voltage (average of VPLUS and VMINUS). Input Current Related Specifications Power Supply Rejection Ratio (PSRR): The input bias currents (IBN and IBI) create voltage - PSRR = (VDD VSS)/ VOST drops across external resistances, which cause VOUT. Input Offset Drift with Temperature ( VOS/ TA): to shift. By convention, the currents going into the pins VPLUS and VMINUS are positive. - Describes how VOST changes with TA;. actually VOST/ TA Traditionally, these physically based currents have - TA is the ambient temperature been mathematically transformed into the equivalent pair of currents IB (input bias current) and IOS (input off- set current).

6 These are the average of IBN and IBI, and their difference, respectively: EQUATION 4: ( I BN + I BI ). I B = -------------------------- 2. I OS = I BN I BI. DS01177A-page 2 2008 Microchip Technology Inc. AN1177. This model makes sense for traditional op amps that CIRCUIT ANALYSIS. have IBN and IBI nearly equal. This means that, in this case, IB is much larger than IOS. This happens because Using a few simple techniques, it is easy to analyze the these currents are caused by similar physically DC error performance of op amp circuits. Several phenomena ( , matched transistor pair with similar common circuits illustrate these techniques. input bias currents). Figure 2 shows how these specified currents are modeled in a circuit. Resistance Seen by the Non-inverting Input VDD. Figure 4 is a simple circuit with a source and several impedances attached to the non-inverting input. The VOST process of calculating the equivalent resistance seen VN.

7 VPLUS by the non-inverting input will be described using this VOUT circuit as the starting point. VMINUS AOL. VI. R1 L1. U1. IB + IOS/2 IB IOS/2 VOUT. V1 C1 R2. VSS. FIGURE 3: Equivalent DC Model for FIGURE 4: Simple Circuit. Traditional Op Amps. The first step is to replace all external components with Some newer op amp architectures have IOS near to the their DC equivalent for a Thevenin analysis: same magnitude as IB. This happens because the Voltage sources become 0V (short circuit). physical causes of IBN and IBI are not physically related Current sources become 0A (open circuit). (they are independent or uncorrelated). Most data Resistors are left as is sheets still use IB and IOS as the specifications. Capacitors become (open circuit). The input currents depend strongly on architecture, Inductors become 0 (short circuit). type of input transistors, and temperature. As discussed before, traditional parts have IB >> IOS.

8 Figure 5 shows the resulting circuit when this is done to Some of the newer architectures have IOS and IB of those components attached to the non-inverting input about the same size. of the op amp in Figure 4. A test source (VX) has been added to help in the Thevenin analysis. Most op amps have ESD diodes at the inputs. PN. junction ESD diodes tend to have small reverse leakage at room temperature. These leakage currents IX. R1. increase by a factor of 2 for each 10 C increase in VX. temperature. Since the ESD diodes tend to match well, the differences between leakage currents tend to be R2. small. These leakage currents are a part of the input bias currents. When an input goes outside the supply voltage(s) the ESD diodes are tied to, the forward FIGURE 5: Equivalent DC Circuit for current can grow to be very large. Non-inverting Input. CMOS inputs transistors have very small input bias The equivalent resistance seen by the non-inverting currents.

9 Most of these op amps use ESD diodes at the input, for this example, is: input for protection; the reverse leakage currents of these ESD diodes are the dominant input bias currents. EQUATION 5: Electrometer grade op amps minimize input currents. They typically use FET transistors at the input that give V. R NEQ = -----X- currents in the femto-ampere (1015A) range. IX. Bipolar inputs have larger input bias currents. They are = R 1 || R 2. the input differential pair's base currents, which do not change much with supply voltage. They will change This resistance is used in the error calculations for the significantly with temperature ( , a 4 range non-inverting bias current (IBN) source. Figure 6 shows between -40 C and +125 C). These op amps usually how this is accomplished; the error at the op amp input use ESD diodes, which increase the bias currents;. is calculated at this point of the process. especially at high temperatures.

10 2008 Microchip Technology Inc. DS01177A-page 3. AN1177. IBN U1 IX. VX. VIBN VOUT. RNEQ R3. R2. VIBN = -IBN RNEQ. FIGURE 6: Application to Non-inverting FIGURE 9: Equivalent DC Circuit for the Bias Current Error Calculations. Inverting Input. The error voltage (VIBN) shown in Figure 6 can be The equivalent resistance seen by the inverting input, placed in an equivalent circuit diagram that does not for this example, is: explicitly show the current IBN. This will make the analysis easier, and more consistent, in later steps. EQUATION 6: This new equivalent circuit is shown in Figure 7 (IBN is already included in VIBN). The VIBN source, when it is V. R IEQ = -----X- positive, will produce a positive change in VOUT. IX. = R 2 || R 3. 0 U1. This resistance is used in the error calculations for the VOUT inverting bias current (IBI) source. Figure 10 shows R1 L1 VIBN. how this is done for the error at the op amp output, referred to the input.