Parallel-Resonant .Converter c tap - BGU

1 NOMENCLATUREAmcCapacitive-Loaded Push-PullParallel- resonant .ConverterCoCrfoscfrIsiLDANIEL EDRYSAM BEN-YAAKOVBen-Gurion University of the NegeviL(I-1V)ipResults of a theoretical and experimental investigation of acapacitive-Ioaded push-pull Parallel-Resonant dc-dc converter (CL-PPRC) are presented and discussed. The push-pnllparalIel- resonant converter (PPRC) is driven by a lower thanresonance frequency and the secondary voltage is rectified andsmoothed by a capacitive fllter- The CL-PPRC is shown to operatein the zero voltage switching (ZVS) mode with a boost-!ike dctransfer ratio which is approximately linear with the period orthe switching frequency. Experimental results of a 180 W, highoutput voltage ( KV) prototype where found to be in goodagreement with the analytical analysis, ID>dels, and simulationresults presented in this work. The basic characteristic of ZVS, thefact that the resonant current is passing through the switches onlyduring a fraction of the period; the high voltage transfer ratio,and the inherent input/output isolation, make the newly proposedtopology a viable design alternative in avionic and p(I-IV)h,ivlinIp,LLiDLrL~rMnp ,TsVcvc(1-IV)VcVpkVdsVgsVinVoV.

2 Z,.Manuscript ~ceived June 23, 1992; revised September 17, Log No. T -AESfl9/4 research was conducted in cooperation and support of theHigh-Voltage Systems Department, ELTA Ltd., Israel AircraftIndustries Ltd., Ashdod, ' add= Department of Electrical and ComputerEngineering, Ben-Gurion University of the Negev, Box 653,Beer-Sheva, ,OOl8-925l1'931'$ @ 1993 IEEEPeak amplitude of parasitic oscillationsat center tapResonant capacitor, reflected to centertapOutput capacitorResonant capacitorOscillation frequencyResonance frequencySwitching frequencyResonant inductor current, reflected tocenter tapiL in phases I-IVCurrent of output transformer,reflected to center tapi p in phases I-IVResonant inductor currentParasitic inductance (L~r) currentDC Input currentCurrent source of parasitic resonancetankResonant inductor, reflected to centertapInput inductorResonant inductorParasitic inductance of outputtransformer, reflected to center tapDC transfer ratio (Vo/Vin)

3 Output transformer transfer ratio&timated practical upper limit ofpower levelLoad resistanceMOSFET's drive transfom1erOutput transformerSelf oscillation time period, 1/ I~c,(~tl + ~t2 + ~t3)Resonance time period, 1/ f, (for noload Tosc = Tr)Switching time period, 1/ IsCenter tap voltage (related to ground)Vc in phases I-IVAverage voltage at center tapPeak amplitude of VrDrain to source voltage .Gate to source voltageDC input voltageDC output voltageVoltage across the resonant network(Lr,Cr)..Characteristic impedance of resonantnetworkCharacteristic impedance of parasiticresonant networkTime interval of phases I-IVResonance angular frequency, 211" f,IEEE 'IRANSAC11 ONS ON AEROSPACE AND ELEC1 RONIC SYSTEMS VOL. 29, OCTOBER 19931287vdsl(I)(1I)II. INTRODUCTION. , ': ; .The search for smaller and yet highly efficientdc-dc converters has lead investigators to 'examineresonant [1] and q uasi- resonant [2] topologies.

4 Theinherent feature of these approaches is the reductionof switching losses at high frequencies by ensuring zerocurrent or zero vo1tag~ switching (ZVS). The resonanttopologies proposed hitherto have, however, a majordrawback: the fact that the resonant current is passingthrough the switches. This shortcoming is alleviatedto a large extent in the push-pull parallel -resonantconverter (PPRC) topology which has been presentedearlier [3-5]. This topology has some similarity to theclassical current fed inverter [6] and to the PPRC [7]described by main advantage of the parallel resonantconverter configuration is the fact that the resonantcurrent can be locked during most of the switchingcycle to within the parallel LC network. Consequently,the heavy resonant current does not pass through theswitches during the complete cycle and the conductionlosses are therefore lower. When the switchingfrequ~ncy is approaching the resonant frequency theswitches are completely free of the resonant current[3, 4].

5 This feature and the inherent nature of zvsof the PPRC make it a viable candidate for highfrequency PPRC topologies discussed earlier wereapplied as a dc-dc transformer with a fixed "dc"transfer ratio [3-5]. It was also demonstrated that avariable transfer ratio can be achieved by a PWM-like(pulsewidth modulation) operation carried on packetsof synchronously rectified sinusoidal signals [3]. Themain disadvantage of this approach is the relativelylow frequency of the resulting PWM waveform whichcalls for heavy output filtering, loosing thereby themain advantages of the high switching frequency ofthe this study we propose a new modification tothe PPRC topology: the capacitive loaded push-pullparallel- resonant converter (CL-PPRC) in which thedc transfer ratio 'is variable. Unlike the case of thesynchronously rectified dc-dc converter describedearlier [3], the new topology maintains the highfrequency baseband throughout The proposedtopology has many features that make it especiallysuitable for the design of dc-dc converters for highoutput voltage.

6 This study was inspired, in fact, by aneed for high voltage supply for avionic application.~J,~I. PROPOSED TOPOLOGYThe basic PPRC power stage of Fig. 1 is builtaround a configuration (Ql, Q2) and aresonant network (Lr,Cr). The power stage is drivenby a square wave (fs) such that, Is :::;: fosc (1)where fosc is the self-oscillating frequency of signal generated by the power stage is coupledto the secondary side via an isolating transformer (T 2in Fig. 1), rectified, and filtered by an RC is shown, this filter arrangement makes the voltagetransfer ratio of the CL-PPRC dependent on thedriving frequency ( ). The behavior of the CL-PPRCis dramatically different from the LCR-loaded onewhose voltage transfer ratio;is independent of thedriving frequency [3-5]..Unloaded power stage: The fundamental featuresof the PPRC are described by considering the caseof the unloaded PPRc, that is, when T2 (Fig.)

7 1)is disconnected. If the condition of (1) holds, andassuming ( 4 Lin > Lr) the expected voltages acrossthe switches will be as shown in Fig. 2 For each halfcycle of the switching frequency ( ) we recognize twophases: a resonant phase (I) and a boost phase (II)(Fig. 3). In the resonant phase (phase I) one transistor,IEEE TRANSACTIONS ON AEROSPACE AND ELEC1 RONIC SYSTEMS VOL. 29, OCTOBER 19931288-(I)(II)I. ip01 -~f]..+ 'L V Yo + RoYm! L: C~ c 2n -W(III)(IV) Q2, is conducting while the other one is in cutoff. Consequently, the voltage of Vds, (Fig. 2) followsthat of a sinusoidal wave with a basic frequency ofC/r). Since Is < Ir (equation (1)), Vds, reaches zerobefore the transistors are toggled. Once the voltageof Vds, becomes negative, the antiparallel diode (Dl)starts conducting and the power stage enters phase(II). In this phase, the inductor (Lr) and capacitor(Cr) are effectively shorted to ground at their bothends (through Q2 and Dl).

8 Consequently, LiD is infact shorted to ground, resembling the boost the toggle instance Ts/2 (Ts = I/Is), Q2 is driveninto cut-off while Ql is driven into conduction and thepower stage enters again phase (I) for the second halfcycle of Is. It should be noted that at the beginning ofphase (I) the voltage of the resonant capacitor (Cr) iszero. Consequently, Q2 switching from "on" to "off'is carried out at zero voltage. Similarly, Ql switchesfrom off (but with a conducting Dl) to on at zerovoltage. That is, the PPRC operation is characterizedby ZVS. The expected voltage across the tank are halfsinewaves (Fig. 2) separated by a dead time of zerovoltage across both "steady state" peak voltage across the tankcan be derived by applying the constraint that thesteady state average voltage at the primary center tapof Ti (Vc) (Fig. 1) must be equal to ViD [4, 5]. This isa consequence of the fact that, if finite currents areassumed, the average voltage across the inductor mustbe zero.

9 Hence= Vin(2)from BASIC EQUATIONS(3)The continuous time equations of the four stages ofthe CL-PPRC were developed under two ) Iin and Vo do not change appreciably during onecycle. Therefore, the input inductor and the outputcapacitor are considered to be a current source and avoltage source, respectively.(4) ;T,..CR-/oaded PPRC: When the load is connected tothe PPRC via a capacitive filter (Fig. I) we distinguish1289 EDRY & BEN -YAAKOV: CAPACmvE-LOADED PUSH-PUU. CONVERrERThe intervals of the four phases are found by equatingthe boundary values of the explicit solutions (AppendixC):2) The forced switching frequenc;y (fs) is lowerthan the self-oscillating frequenc;y (fosc) (Fig. 4), :(5)Ts ~ the results of the detailed derivationgiven in Appendix B:sin-1(A2)ll l = 1- 0 = ~"'rll 2 = 2 - 1 = A1 COS("'r~ UA2 Zrt E (to,q)t E (t1,t2)t E (t2,t3)t E (t3,t4)~=A2W,(6)vc(t) =A1 Sin(Wr(t- to));A2;A2 COS(Wr(t -!)

10 2));0;Ts-T~27rAt3=t3-t2 = ~ = t4 -t3 = 2- (Atl + At2 + At3) =( E (01(1)( E (11(2) (7)( E (2,(3)( E (3,(4)iL(t) =Iin -A3 COS("',(t -to));A4(t -tu + As;Iin + A6sin(",!(t -t2));A7;t E (tl,t2)elsewhereAs -A4(t -t1);0;v. STEADY STATE TRANSFER FUNCTION OFCL-PPRC ,(8)ip(t) =whereVoAt = 2 IinZr + 2;;(9)(10)But,(11)i7;'2112 v c(I)(t) dt +II1'1 vc(t)dt =10Vc(II)(t)dt(12)where(13)VoA6 = 2nz;11114 vc([)(t) dt = Al sin(lJ)rt) dt10 10Al= -(1- COs(lJ) )IJ)rllzllz vc([[)(t)dt = A2dt = 4Al= -COs(lJ) )IJ)r113 13 .vc([[[)(t)dt = (lJ)rt)dt =IZ IZ .which implies(14)VoA2(15)A7 = fin + Zr~.A. ==~v ,+l~ or nz;(16) ZrZr = I 1--IJJr -~LrL=4C = 4Cr.(2~)(17)(18)(19)(31)(20)IEEE TRANSACTIONS ON AEROSPACE AND SYSTEMS VOL 29, OCTOBER 19931290(32) no loss conditionsl:~ = VoloV2-2---~.). )Vin the transfer ratio (M)]:1:M-o=v:.Equation (33) can thus be rewritten asM2 Vin(34)Vc-~!:j\i"!\-1v\j.]]]]]