PCM1808 Single-Ended, Analog-Input 24-Bit, 96 …

1 AntialiasLPFBCKR eferenceDelta-SigmaModulator1 / 64 DecimationFilterWithHigh-PassFilterPower SupplyAGNDDGNDC lock and Timing ControlLRCKDOUTSCKIS erialInterfaceMode/FormatControlFMTMD1MD 0 AntialiasLPFD elta-SigmaModulator1V LINVREFV RINVCCVDDP roductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityReferenceDesignPCM1808 SLES177B APRIL2006 REVISEDAUGUST2015 PCM1808 Single-Ended, analog -Input24-Bit,96-kHzSt ereoADC1 Features2 Applications1 24-BitDelta-SigmaStereoA/D Converter(ADC) DVDR ecorder single -EndedVoltageInput:3 Vp-p DigitalTV HighPerformance: AV Amplifieror Receiver MD Player THD+N: 93 dB (Typical) CD Recorder SNR:99 dB (Typical) MultitrackReceiver DynamicRange:99 dB (Typical) ElectricMusicalInstrument OversamplingDecimationFilter: OversamplingFrequency: 643 Description Pass-BandRipple: a high-performance,low- Stop-BandAttenuation: 65 dBcost, single -chip,stereoanalog-to-digit alconverter On-ChipHigh- (48 kHz) delta-sigmamodulatorwith FlexiblePCMA udioInterface64-timesoversamplingandincl udesa digital Master-or Slave-ModeSelectabledecimationfilterand high-passfilterthat removesthe DataFormats.

2 24-BitI2S, 24-BitLeft-Justifieddc componentof ,the PCM1808devicesupportsmaster PowerDownand Resetby HaltingSystemClockand slavemodeand two dataformatsin serialaudio AnalogAntialiasLPF Includedinterface. SamplingRate:8 kHz 96 kHzThe PCM1808devicesupportsthe power-downand SystemClock:256 fS, 384 fS, 512 fSresetfunctionsby meansof haltingthe systemclock. Resolution:24 BitsThe PCM1808deviceis suitablefor widevarietyof DualPowerSupplies:cost-sensitiveconsumer applicationsrequiringgood 5-V for Analogperformanceand operationwith a 5-V analogsupplyand the PCM1808 Digitaldeviceusesa Package:14-PinTSSOP deviceis availablein a small, (1)PARTNUMBERPACKAGEBODYSIZE(NOM) PCM1808 TSSOP(14) (1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand APRIL2006 Applicationand Pin Configurationand Deviceand Mechanical,Packaging,and RevisionHistoryChangesfromRevisionA (August2006)

3 To RevisionBPage AddedESDR atingstable,FeatureDescriptionsection,De viceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and 2006 2015, APRIL2006 REVISEDAUGUST20155 Pin Configurationand Functions14-PinTSSOPPW PackageTop ViewPin FunctionsPINI/ODESCRIPTIONNAMEPINAGND2 AnalogGNDBCK8I/OAudio-databit-clockinput or output(1)DGND5 DigitalGNDDOUT9 OAudio-datadigitaloutputFMT12 IAudio-interfaceformatselect(2)LRCK7I/OA udio-datalatch-enableinputor output(1)MD010 IAudio-interfacemodeselect0(2)MD111 IAudio-interfacemodeselect1(2)SCKI6 ISystemclockinput;256 fS, 384 fSor 512 fS(3)VCC3 Analogpowersupply,5-VVDD4 Digitalpowersupply, ,L-channelVINR14 IAnaloginput,R-channelVREF1 Reference-voltagedecoupling(= VCC)(1)Schmitt-triggerinputwith internalpulldown(50-k , typical)(2)Schmitt-triggerinputwith internalpulldown(50-k , typical),5-V tolerant(3)Schmitt-triggerinput,5-V tolerantCopyright 2006 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks.

4 PCM1808 PCM1808 SLES177B APRIL2006 (unlessotherwisenoted)(1)MINMAXUNITVCCA nalogsupplyvoltage ,DGND ,BCK,DOUT (VDD+ V) < 4 VDigitalinputvoltageSCKI,MD0,MD1,FMT , VINR,Analoginputvoltage (VCC+ V) < (anypins exceptsupplies) 10mATJJ unctiontemperature150 CTstgStoragetemperature 55150 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions. Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay (HBM),per ANSI/ESDA/JEDECJS-001,all pins(1) 4000V(ESD)ElectrostaticdischargeVCharged -devicemodel(CDM),per JEDEC specificationJESD22-C101, 1500all pins(2)(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.

5 (2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (unlessotherwisenoted)MINNOMMAXUNITVCCA nalogsupplyvoltage(seePowerSupplyRecomme ndations) ,full scale( 0 dB)VCC= 5 V3Vp-pVIH(1)Highinputlogiclevel2 VDDVDCVIL(1)Low (2) (3) (2) (3)Low compatibleDigitalinputclockfrequency, ,samplingclock896kHzDigitaloutputload capacitance20pFTAO peratingambienttemperaturerange 4085 CTJJ unctiontemperature150 C(1)Pins7, 8: LRCK,BCK(Schmitt-triggerinput,with 50-k typicalpulldownresistor,in slavemode)(2)Pin 6: SCKI(Schmitt-triggerinput,5-V tolerant)(3)Pins10 12: MD0,MD1,FMT(Schmitt-triggerinput,with 50-k typicalpulldownresistor,5-V tolerant)4 SubmitDocumentationFeedbackCopyright 2006 2015, APRIL2006 (1)PW (TSSOP)UNIT14 PINSR C/WR JC(top)Junction-to-case(top) C/WR C/W C/W C/WR JC(bot)Junction-to-case(bottom)thermalre sistanceN/A C/W(1)

6 For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport, specificationsat TA= 25 C, VCC= 5 V, VDD= V, mastermode,fS= 48 kHz,systemclock= 512 fS, 24-bitdata,unlessotherwisenotedPARAMETER TESTCONDITIONSMINTYPMAXUNITR esolution24 BitsDATAFORMATA udiodatainterfaceformatI2S, left-justifiedAudiodatabit length24 BitsAudiodataformatMSB-first,2s complementfSSamplingfrequency84896kHz256 (1)Highinputlogiclevel2 VDDVDCVIL(1)Low (2) (3) (2) (3)Low (2)HighinputlogiccurrentVIN= VDD 10 AIIL(2)Low inputlogiccurrentVIN= 0 V 10 AIIH(1) (3)HighinputlogiccurrentVIN= VDD65100 AIIL(1) (3)Low inputlogiccurrentVIN= 0 V 10 AOUTPUTLOGICVOH(4)HighoutputlogiclevelIO UT= 4 (4)Low outputlogiclevelIOUT= 4 ACCURACY% ofGainmismatch,channel-to-channel 1 3 FSR% ofGainerror 3 6 FSR(1)Pins7, 8: LRCK,BCK(Schmitt-triggerinput,with 50-k typicalpulldownresistor,in slavemode)(2)Pin 6: SCKI(Schmitt-triggerinput,5-V tolerant)(3)Pins10 12: MD0,MD1,FMT(Schmitt-triggerinput,with 50-k typicalpulldownresistor,5-V tolerant)(4)Pins7 9: LRCK,BCK(in mastermode),DOUTC opyright 2006 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks.

7 PCM1808 PCM1808 SLES177B APRIL2006 (continued)All specificationsat TA= 25 C, VCC= 5 V, VDD= V, mastermode,fS= 48 kHz,systemclock= 512 fS, 24-bitdata,unlessotherwisenotedPARAMETER TESTCONDITIONSMINTYPMAXUNITDYNAMICPERFOR MANCE(5)VIN= dB, fS= 48 kHz 93 87 VIN= dB, fS= 96 kHz(6) 87 THD+NTotalharmonicdistortion+ noisedBVIN= 60 dB, fS= 48 kHz 37 VIN= 60 dB, fS= 96 kHz(6) 39fS= 48 kHz,A-weighted9599 DynamicrangedBVDCfS= 96 kHz,A-weighted(6)101fS= 48 kHz,A-weighted9599S/NSignal-to-noiserati odBfS= 96 kHz,A-weighted(6)101fS= 48 kHz9397 ChannelseparationdBfS= 96 kHz(6) VCCVp-pCentervoltage(VREF) VCCVI nputimpedance60k Antialiasingfilter frequencyresponse 3 3 dB1000 POWERSUPPLYREQUIREMENTSfS= 48 kHz,96 kHz(6) (7)Powereddown(8)1 AfS= 48 (7)fS= 96 kHz(6) (8)150 AfS= 48 kHz6281mWPowerdissipation(7)fS= 96 kHz(6)77 Powereddown(8)500 W(5)Testingof analogperformancespecificationsusesan audiomeasurementsystemby AudioPrecision with 400-HzHPFand 20-kHzLPF in RMSmode.

8 (6)fS= 96 kHz,systemclock= 256 fS.(7)Minimumload on LRCK(pin 7), BCK(pin 8), DOUT(pin 9)(8)Power-downand resetfunctionsenabledby haltingSCKI,BCK, 2006 2015, VSCKI2 Vtw(SCKL)tw(SCKH) APRIL2006 (SCKH)Systemclockpulseduration,HIGH8nstw (SCKL)Systemclockpulseduration,LOW8nsSys temclockduty cycle40%60%CLOCK-HALTPOWER-DOWNANDRESETT IMINGt(CKR)Delaytime fromSCKI halt to internalreset4 st(RST)Delaytime fromSCKI resumeto resetrelease1024 SCKI st(REL)Delaytime fromresetreleaseto DOUT output8960/ fS sAUDIODATAINTERFACETIMING(SlaveMode:LRCK and BCKW orkas Inputs)(1)t(BCKP)BCKperiod1 / (64 fS)nst(BCKH)BCKpulseduration, t(SCKI)nst(BCKL)BCKpulseduration, t(SCKI)nst(LRSU)LRCK setuptime to BCKrisingedge50nst(LRHD)LRCK hold time to BCKrisingedge10nst(LRCP)LRCH period10 st(CKDO)Delaytime,BCKfallingedgeto DOUT valid 1040nst(LRDO)Delaytime,LRCK edgeto DOUT valid 1040nstrRisetime of all signals20nstfFall time of all signals20nsAUDIODATAINTERFACETIMING(Mast erMode.)

9 LRCKand BCKW orkas Outputs)(2)t(BCKP)BCKperiod1501 / (64 fS)2000nst(BCKH)BCKpulseduration,HIGH651 200nst(BCKL)BCKpulseduration,LOW651200ns t(CKLR)Delaytime,BCKfallingedgeto LRCK valid 1020nst(LRCP)LRCK period101 / fS125nst(CKDO)Delaytime,BCKfallingedgeto DOUT valid 1020nst(LRDO)Delaytime,LRCK edgeto DOUT valid 1020nstrRisetime of all signals20nstfFall time of all signals20nsAUDIOCLOCKINTERFACETIMING(Mas terMode:BCKW orkas Outputs)(3)t(SCKBCK)Delaytime,SCKI risingedgeto BCKedge530ns(1)Timingmeasurementreferenc elevelis V for inputand VDDfor fall timesare from10%to 90%of the DOUTis 20 pF. t(SCKI)is the SCKI period.(2)Timingmeasurementreferenceleve lis VDD. Riseand fall timesare from10%to 90%of the all signalsis 20 pF.

10 (3)Timingmeasurementreferencelevelis V for inputand VDDfor BCKis 20 pF. This timingapplieswhenSCKI frequencyis less than25 SystemClockTimingCopyright 2006 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks:PCM18081024 System ClocksResetReset VVDDI nternalResetSystemClockDOUTZero DataNormal Data8960/fS48/fINor 48/fSFade-In StartFade-In CompleteOperationDOUT(Contents)BPZPCM180 8 SLES177B APRIL2006 Power-OnTiming8 SubmitDocumentationFeedbackCopyright 2006 2015,TexasInstrumentsIncorporatedProduct FolderLinks: PCM1808 BCKLRCKDOUTt(BCKH)t(BCKL)t(LRHD)t(LRSU)t (BCKP)t(CKDO)t(LRDO) Vt(LRCP)Clock-Halt ResetSCKI48/fINor 48/fSFade-In StartFade-In CompleteInternalResetOperationOperationD OUTN ormal DataNormal DataDOUT(Contents)Normal DataSCKI HaltSCKI ResumeFixed to Low or Hight(CKR)Reset: t(RST)Reset Release: t(REL)BPZZero APRIL2006 REVISEDAUGUST2015 Figure3.