PIC16F88X Errata - Microchip Technology

1 2007-2014 Microchip Technology 1 PIC16F88 XThe PIC16F88X family devices that you have receivedconform functionally to the current Device Data Sheet(DS41291G), except for the anomalies described inthis document. The silicon issues discussed in the following pages arefor silicon revisions with the Device and Revision IDslisted in Ta b l e 1. The silicon issues are summarized inTable 2, Table 3 and Table Errata described in this document will be addressedin future revisions of the PIC16F88X Sheet clarifications and corrections start on page14, following the discussion of silicon silicon revision level can be identified using thecurrent version of MPLAB IDE and Microchip sprogrammers, debuggers, and emulation tools, whichare available at the Microchip corporate web site( ).For example, to identify the silicon revision levelusing MPLAB IDE in conjunction with a the appropriate interface, connect thedevice to the hardware an MPLAB IDE the MPLAB IDE project for theappropriate device and hardware on the version of MPLAB IDE you areusing, do one of the following:a) For MPLAB IDE 8, select Programmer > ) For MPLAB X IDE, select Window >Dashboard and click the Refresh DebugTool Status icon ().

2 On the development tool used, thepart number and Device Revision ID valueappear in the Output DEVREV values for the various PIC16F88X siliconrevisions are shown in Ta b l e 1. Note:This document summarizes all siliconerrata issues from all revisions of silicon,previous as well as current. Only theissues indicated in the last column ofTable 2, Table 3 and Table 4 apply to thecurrent silicon revision (A0 or A2, asapplicable).Note:If you are unable to extract the siliconrevision level, please contact your localMicrochip sales office for 1:SILICON DEVREV VALUESPart NumberDevice ID(1)Revision ID for Silicon Revision(2)A0A2 PIC16F8822000h00hPIC16F8832020h00hPIC16F 8842040h00hPIC16F8862060h02hPIC16F887208 0h02hNote 1:The device and revision data is stored in the Device ID located at 2006h in program :Refer to the PIC16F88X Memory Programming Specification (DS41287) for detailed Family Silicon Errata and Data Sheet ClarificationPIC16F88 XDS80000302J-page 2 2007-2014 Microchip Technology 2:SILICON ISSUE SUMMARY (PIC16F882)ModuleFeatureItem NumberIssue SummaryAffected Revisions(1) using Timer2 of the collision on bit on may take additional may stop running at low the module generates a clock waveforms if dead-band delay is greater than the PWM duty 1:Only those issues indicated in the last column apply to the current silicon revision.

3 2007-2014 Microchip Technology 3 PIC16F88 XTABLE 3:SILICON ISSUE SUMMARY (PIC16F883/PIC16F884)ModuleFeatureItem NumberIssue SummaryAffected Revisions(1) using Timer2 of the collision on bit on may take additional may stop running at low the module generates a clock waveforms if dead-band delay is greater than the PWM duty 1:Only those issues indicated in the last column apply to the current silicon 4 2007-2014 Microchip Technology 4:SILICON ISSUE SUMMARY (PIC16F886/PIC16F887)ModuleFeatureItem NumberIssue SummaryAffected Revisions(1) using Timer2 of the collision on bit on may take additional may stop running at low the module generates a clock waveforms if dead-band delay is greater than the PWM duty read and verify 1:Only those issues indicated in the last column apply to the current silicon revision. 2007-2014 Microchip Technology 5 PIC16F88 XSilicon Errata Issues1.

4 Module: Low-Voltage In-Circuit Serial Programming (LVP)If LVP (Low-Voltage Programming) mode isenabled, programming the device using the VPPpin while holding high or toggling the port pin RB3/PGM during Program mode could disrupt theprogramming aroundPull down pin RB3/PGM using external circuitryduring programming of the Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F8872. Module: MSSP (SPI Mode)When the SPI is using Timer2/2 as the clocksource, a shorter than expected SCK pulse mayoccur on the first bit of the transmitted/receiveddata (Figure 1).FIGURE 1:SCK PULSE VARIATION USING TIMER2/2 Work aroundTo avoid producing the short pulse, turn off Timer2and clear the TMR2 register, load SSPBUF withthe data to transmit and then turn Timer2 back to Example 1 for sample 1:AVOIDING THE INITIAL SHORT SCK PULSEA ffected Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F887 Note:This document summarizes all siliconerrata issues from all revisions of silicon,previous as well as current.

5 Only theissues indicated by the shaded column inthe following tables apply to the currentsilicon revision (A0 or A2, as applicable).A0XA0XA2XA0XA0XA2 XSDOSCKW rite SSPBUFbit 0 = 1bit 1 = 0bit 2 = 1..LOOP BTFSS SSPSTAT, BF ;Data received? ;(Xmit complete?) GOTO LOOP ;No MOVF SSPBUF, W ;W = SSPBUF MOVWF RXDATA ;Save in user RAM MOVF TXDATA, W ;W = TXDATA BCF T2 CON, TMR2ON ;Timer2 off CLRF TMR2 ;Clear Timer2 MOVWF SSPBUF ;Xmit New data BSF T2 CON, TMR2ON ;Timer2 on PIC16F88 XDS80000302J-page 6 2007-2014 Microchip Technology Module: Analog-To-Digital Converter (ADC) ModuleSelecting the VP6 reference as the analog inputsource (CHS<3:0> =1111) for the ADCconversion after sampling another analog channelwith input voltages approximately greater can temporarily disturb the aroundSelect an ADC channel with input voltages lowerthan prior to selecting the VP6 referencevoltage input.

6 Any analog channel can be used,even if that channel is configured as a digital I/O(configured as an output) that is driving the outputpin low. An alternative is to configure the CVREF module to output a voltage lower than andthen selecting that analog channelCHS<3:0> =1110 as the analog input 2:AVOID DISTURBING THE HFINTOSC OSCILLATORA ffected Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F8874. Module: MSSP (SPI Master Mode)With MSSP in SPI Master mode, FOSC/64 orTimer2/2 clock rate and CKE = 0, a write collisionmay occur if SSPBUF is loaded immediately afterthe transfer is complete. A delay may be requiredafter the MSSP Interrupt Flag bit, SSPIF, is set orthe Buffer Full bit, BF, is set and before writingSSPBUF. If the delay is insufficiently short, a writecollision may occur as indicated by the WCOL bitbeing aroundAdd a software delay of one SCK period afterdetecting the completed transfer and prior toupdating the SSPBUF contents.

7 Verify the WCOLbit is clear after writing SSPBUF. If the WCOL isset, clear the bit in software and rewrite theSSPBUF Codes that pertain to this issue:All engineering and production Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F887 Note:This only occurs when selecting the VP6reference ADC channel using theCHS<3:0> bits in the ADCON0 registerand NOT during the start of an actual ADCconversion using the GO/DONE bit in theADCON0 ADCON0 ;MOVLW B XX111001 ;Select ADCMOVWF ADCON0 ;Channel CVREFMOVLW B XX111101 ;Select ADCMOVWF ADCON0 ;Channel VP6A0XA0XA2X 2007-2014 Microchip Technology 7 PIC16F88X5. Module: MSSP (I2C Slave Mode)When the master device wants to terminatereceiving any more data from the slave device, itwill do so by sending a NACK in response to thelast data byte received from the slave. When theslave receives the NACK, the R/W bit of theSSPSTAT register remains set aroundUse the CKP bit of the SSPCON register todetermine when the master has responded with aNACK.

8 The CKP bit will be clear when theresponse is an ACK, and set when the response isa NACK. The CKP bit is automatically cleared tostretch the clock when the master responds toreceived data with an ACK. This gives the slavetime to load the SSPBUF register before settingthe CKP bit to release the clock stretching. Whenthe master responds to received data with aNACK, the CKP bit properly remains set and thereis no clock Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F887A0XA0XA2 XPIC16F88 XDS80000302J-page 8 2007-2014 Microchip Technology Module: MSSP (I2C Master Mode)When the MSSP is I2C Master mode with aslave device stretching the clock, the clockgeneration does not function as described in thedata a slave device is performing clock stretchingby pulling the SCL line low, the master deviceshould continuously sample the SCL line to deter-mine when all slaves have released SCL.

9 WhenSCL is released, the master device should waitone BRG period to ensure a constant SCL current implementation does not ensureaccurate SCL high time. During clock stretch, theMSSP device will erroneously continue runningthe BRG counter. At the end of the clock stretch,the BRG counter continues to count down for theremainder of the BRG period, and then the MSSP device will immediately resume transmitting 1 illustrates an expected I2C transmissionin which the SCL line is completely controlled bythe master device and the slave device does notattempt to stretch the clock 2 illustrates the expected operation of anI2C transmission in which the slave device hasstretched the clock period by holding the SCL linelow. The high time of the SCL pulse is constant,regardless of the duration of the clock 3 and Figure 4 illustrate an actual I2 Ctransmission in which the slave has stretched theclock period by holding the SCL line low.

10 Note thatthe high time of the SCL signal has shortened fromthe expected 1:ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHINGFIGURE 2:EXPECTED OPERATION WITH CLOCK STRETCHING BRG Period BRG Period BRG Period BRG Period BRG Period BRG Period SDA SCL Master Slave BRG Period BRG Period BRG Period BRG Period SDA SCL Master Slave 2007-2014 Microchip Technology 9 PIC16F88 XFIGURE 3:ACTUAL (INCORRECT) OPERATION WITH CLOCK STRETCHING EXAMPLE 1 FIGURE 4:ACTUAL (INCORRECT) OPERATION WITH CLOCK STRETCHING EXAMPLE 2 Work aroundSet the communication speed to match theslowest device on the bus. This ensures that noslave device will perform clock is possible to dynamically adjust thecommunication speed to match the device beingaddressed by modifying the BRG , the behavior of slower slave devicesmust be understood and speed adjustments madesuch that no slave performs clock Silicon RevisionsPIC16F882 PIC16F883/PIC16F884 PIC16F886/PIC16F887 SDA SCL Master Slave BRG Period BRG Period BRG PeriodBRG PeriodBRG Period BRG Period SDA SCL Master Slave BRG Period BRG Period BRG PeriodBRG PeriodBRG Period BRG PeriodA0XA0XA2 XPIC16F88 XDS80000302J-page 10 2007-2014 Microchip Technology Module: MSSPWhen all of the following conditions are met:1.