PIC18F8722 Family Data Sheet - Microchip Technology

1 2008 Microchip Technology FamilyData Sheet64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollerswith 10-Bit A/D and nanoWatt TechnologyDS39646C-page ii 2008 Microchip Technology contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use.

2 Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the and other , Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the Age, Application Maestro, CodeGuard, dsPICDEM, , dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM.

3 PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the and other is a service mark of Microchip Technology Incorporated in the other trademarks mentioned herein are property of their respective companies. 2008, Microchip Technology Incorporated, Printed in the , All Rights Reserved. Printed on recycled the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet . Microchip believes that its Family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

4 There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts.

5 Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

6 2008 Microchip Technology 1 PIC18F8722 FAMILYP ower Management Features: Run: CPU On, Peripherals On Idle: CPU Off, Peripherals On Sleep: CPU Off, Peripherals Off Ultra Low 50 nA Input Leakage Run mode Currents Down to 25 A Typical Idle mode Currents Down to A Typical Sleep mode Current Down to 120 nA Typical Timer1 Oscillator: 900 nA, 32 kHz, 2V Watchdog Timer: A, 2V Typical Two-Speed Oscillator Start-upFlexible Oscillator Structure: Four Crystal modes, up to 40 MHz 4x Phase Lock Loop (PLL) Available for Crystal and Internal Oscillators Internal Oscillator Block:- Fast wake from Sleep and Idle, 1 s typical- Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL- User-tunable to compensate for frequency drift Secondary oscillator using Timer1 @ 32 kHz Fail-Safe Clock Monitor:- Allows for safe shutdown if peripheral clock stopsPeripheral Highlights: High-Current Sink/Source 25 mA/25 mA Three Programmable External Interrupts Four Input Change Interrupts Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only):- One, two or four PWM outputs- Programmable dead time- Auto-shutdown and auto-restartPeripheral Highlights (Continued).

7 Up to 2 Capture/Compare/PWM (CCP) modules, one with Auto-Shutdown (28-pin devices) Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C Master and Slave modes Enhanced Addressable USART module:- Supports RS-485, RS-232 and LIN/J2602- RS-232 operation using internal oscillator block (no external crystal required) 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter module:- Conversion available during Sleep dual Analog Comparators with Input Multiplexing Programmable 16-Level High/Low-Voltage Detection (HLVD) moduleSpecial Microcontroller Features: C Compiler Optimized Architecture 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical 1,000,000 Erase/Write Cycle Data EEPROM Memory Typical Flash/Data EEPROM Retention: 100 Years Typical Self-Programmable under Software Control Priority Levels for Interrupts 8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT):- Programmable period from 4 ms to 131s Single-Supply 5V In-Circuit Serial Programming (ICSP ) via Two Pins In-Circuit Debug (ICD) via Two Pins Wide Operating Voltage Range.

8 To Programmable Brown-out Reset (BOR) with Software Enable OptionDeviceProgram MemoryData MemoryI/O10-BitA/D (ch)CCP/ECCP(PWM)MSSPEUSARTC omparatorsTimers8/16-BitExternal BusFlash(bytes)# Single-WordInstructions SRAM(bytes)EEPROM(bytes)SPIM asterI2C PIC18F652748K245763936102454122/32YY222/ 3 NPIC18F662264K327683936102454122/32YY222 /3 NPIC18F662796K491523936102454122/32YY222 /3 NPIC18F6722128K655363936102454122/32YY22 2/3 NPIC18F852748K245763936102470162/32YY222 /3 YPIC18F862264K327683936102470162/32YY222 /3 YPIC18F862796K491523936102470162/32YY222 /3 YPIC18F8722128K655363936102470162/32YY22 2/3Y64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with10-Bit A/D and nanoWatt TechnologyPIC18F8722 FAMILYDS39646C-page 2 2008 Microchip Technology Diagrams Note 1.

9 The ECCP2/P2A pin placement is determined by the CCP2MX Configuration 4917 18 19 20 21 22 23 24 25 26RE2/CS/P2 BRE3/P3 CRE4/P3 BRE5/P1 CRE6/P1 BRE7/ECCP2(1)/P2A(1)RD0/PSP0 VDDVSSRD1/PSP1RD2/PSP2RD3/PSP3RD4/PSP4/S DO2RD5/PSP5/SDI2/SDA2RD6/PSP6/SCK2/SCL2R D7/PSP7/SS2RE1/WR/P2 CRE0/RD/P2 DRG0/ECCP3/P3 ARG1/TX2/CK2RG2/RX2/DT2RG3/CCP4/P3 DRG5/MCLR/VPPRG4/CCP5/P1 DVSSVDDRF7/SS1RF6/AN11RF5/AN10/CVREFRF4/ AN9RF3/AN8RF2/AN7/C1 OUTRB0/INT0RB1/INT1RB2/INT2RB3/INT3RB4/K BI0RB5/KBI1/PGMRB6/KBI2/PGCVSSOSC2/CLKO/ RA6 OSC1/CLKI/RA7 VDDRB7/KBI3/PGDRC4/SDI1/SDA1RC3/SCK1/SCL 1RC2/ECCP1/P1 ARF0/AN5RF1/AN6/C2 OUTAVDDAVSSRA3/AN3/VREF+RA2/AN2/VREF-RA1 /AN1RA0/AN0 VSSVDDRA4/T0 CKIRA5/AN4/HLVDINRC1/T1 OSI/ECCP2(1)/P2A(1)RC0/T1 OSO/T13 CKIRC7/RX1/DT1RC6/TX1/CK1RC5/SDO11516314 03927 28 29 3032484746454443424154 53 52 5158 57 56 5560 5964 63 62 6164-Pin TQFPPIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 2008 Microchip Technology 3 PIC18F8722 FAMILYPin Diagrams (Continued)PIC18F85273456789101112131415 164847464544434241403964 63 62 6121 22 23 24 25 26 27 28 29 30 31 32RE2/AD10/CS/P2 BRE3/AD11/P3C(2)RE4/AD12/P3B(2)RE5/AD13/ P1C(2)RE6/AD14/P1B(2)RE7/AD15/ECCP2(1)/P 2A(1)

10 RD0/AD0/PSP0 VDDVSSRD1/AD1/PSP1RD2/AD2/PSP2RD3/AD3/PS P3RD4/AD4/PSP4/SDO2RD5/AD5/PSP5/SDI2/SDA 2RD6/AD6/PSP6/SCK2/SCL2RD7/AD7/PSP7/SS2R E1/AD9/WR/P2 CRE0/AD8/RD/P2 DRG0/ECCP3/P3 ARG1/TX2/CK2RG2/RX2/DT2RG3/CCP4/P3 DRG5/MCLR/VPPRG4/CCP5/P1 DVSSVDDRF7/SS1RB0/INT0RB1/INT1RB2/INT2RB 3/INT3/ECCP2(1)/P2A(1)RB4/KBI0RB5/KBI1/P GMRB6/KBI2/PGCVSSOSC2/CLKO/RA6 OSC1/CLKI/RA7 VDDRB7/KBI3/PGDRC4/SDI1/SDA1RC3/SCK1/SCL 1RC2/ECCP1/P1 ARF0/AN5RF1/AN6/C2 OUTAVDDAVSSRA3/AN3/VREF+RA2/AN2/VREF-RA1 /AN1RA0/AN0 VSSVDDRA4/T0 CKIRA5/AN4/HLVDINRC1/T1 OSI/ECCP2(1)/P2A(1)RC0/T1 OSO/T13 CKIRC7/RX1/DT1RC6/TX1/CK1RC5/SDO1RJ0/ALE RJ1/OERH1/A17RH0/A1612RH2/A18RH3/A191718 RH7/AN15/P1B(2)RH6/AN14/P1C(2)RH5/AN13/P 3B(2)RH4/AN12/P3C(2)RJ5/CERJ4/BA037RJ7/U BRJ6/LB5049RJ2/WRLRJ3/WRH192033 3435 36385857565554535251605968 67 66 6572 71 70 6974 7378 77 76 75798080-Pin TQFPNote 1:The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode : P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration FAMILYDS39646C-page 4 2008 Microchip Technology of Overview.