PICmicro Mid-Range MCU Family Reference Manual

1 M 1997 Microchip Technology 1997 /DS33023A PICmicro Mid-Range MCU FamilyReference Manual M December 1997 /DS33023A 1997 Microchip Technology Inc. Internationally Recognized Quality System Certifications Microchip s Quality System embodies the requirementsof ISO9001:1994. Our Microchip Chandler and TempeDesign and Manufacturing facilities have been certifiedto ISO 9001. The Microchip Kaohsiung Test facility, andprimary Assembly houses have been certified to ISO9002. ISO certification plans are in-process for an esti-mated certification grant by year-end 1997. In addition,Microchip has received numerous customer certifica-tions, including a Delco issued certificate of complianceto AEC-A100/QS9000. Microchip received ISO 9001 Quality System certifica-tion for its worldwide headquarters, design, and waferfabrication facilities in January, 1997.

2 Our field-pro-grammable PICmicro 8-bit MCUs, Serial EEPROMs,related specialty memory products and developmentsystems conform to the stringent quality standards ofthe International Standard Organization (ISO). All rights reserved. Copyright 1997, Microchip TechnologyIncorporated, USA. Information contained in this publicationregarding device applications and the like is intended throughsuggestion only and may be superseded by updates. No rep-resentation or warranty is given and no liability is assumed byMicrochip Technology Incorporated with respect to the accu-racy or use of such information, or infringement of patents orother intellectual property rights arising from such use or oth-erwise. Use of Microchip s products as critical components inlife support systems is not authorized except with expresswritten approval by Microchip.

3 No licenses are conveyed,implicitly or otherwise, under any intellectual property Microchip logo and name are registered trademarks ofMicrochip Technology Inc. in the and other rights reserved. All other trademarks mentioned herein arethe property of their respective companies. No licenses areconveyed, implicitly or otherwise, under any intellectual prop-erty rights. Trademarks The Microchip name, logo, PIC, K EE L OQ , PICMASTER,PICSTART, PRO MATE, and SEEVAL are registeredtrademarks of Microchip Technology Incorporated in , PICmicro , ICSP and In-Circuit Serial Programmingare trademarks of Microchip Technology Quick-Turn Production is a Service Mark of Micro-chip Technology other trademarks mentioned herein are property of theirrespective companies. 1997 Microchip Technology iii M PAGE SECTION 1.

4 INTRODUCTION 1-1 Introduction .. 1-2 Manual Objective .. 1-3 Device Structure .. 1-4 Development Support .. 1-6 Device Varieties .. 1-7 Style and Symbol Conventions .. 1-12 Related Documents .. 1-14 Related Application Notes .. 1-17 Revision History .. 1-18 SECTION 2. OSCILLATOR 2-1 Introduction .. 2-2 Oscillator Configurations .. 2-2 Crystal Oscillators / Ceramic Resonators .. 2-4 External RC Oscillator .. 2-12 Internal 4 MHz RC Oscillator .. 2-13 Effects of Sleep Mode on the On-chip Oscillator .. 2-17 Effects of Device Reset on the On-chip Oscillator .. 2-17 Design Tips .. 2-18 Related Application Notes .. 2-19 Revision History .. 2-20 SECTION 3. RESET 3-1 Introduction .. 3-2 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER) .. 3-4 Registers and Status Bit Values.

5 3-10 Design Tips .. 3-16 Related Application Notes .. 3-17 Revision History .. 3-18 SECTION 4. ARCHITECTURE 4-1 Introduction .. 4-2 Clocking Scheme/Instruction Cycle .. 4-5 Instruction Flow/Pipelining .. 4-6I/O Descriptions .. 4-7 Design Tips .. 4-12 Related Application Notes .. 4-13 Revision History .. 4-14 Table of Contents DS00097D-page iv 1997 Microchip Technology Inc. M PAGE SECTION 5. CPU AND ALU 5-1 Introduction .. 5-2 General Instruction Format .. 5-4 Central Processing Unit (CPU) .. 5-4 Instruction Clock .. 5-4 Arithmetic Logical Unit (ALU) .. 5-5 STATUS Register .. 5-6 OPTION_REG Register .. 5-8 PCON Register .. 5-9 Design Tips .. 5-10 Related Application Notes .. 5-11 Revision History .. 5-12 SECTION 6. MEMORY ORGANIZATION 6-1 Introduction .. 6-2 Program Memory Organization .. 6-2 Data Memory Organization .. 6-8 Initialization.

6 6-14 Design Tips .. 6-16 Related Application Notes .. 6-17 Revision History .. 6-18 SECTION 7. DATA EEPROM 7-1 Introduction .. 7-2 Control Register .. 7-3 EEADR .. 7-4 EECON1 and EECON2 Registers .. 7-4 Reading the EEPROM Data Memory .. 7-5 Writing to the EEPROM Data Memory .. 7-5 Write Verify .. 7-6 Protection Against Spurious Writes .. 7-7 Data EEPROM Operation During Code Protected Configuration .. 7-7 Initialization .. 7-7 Design Tips .. 7-8 Related Application Notes .. 7-9 Revision History .. 7-10 SECTION 8. INTERRUPTS 8-1 Introduction .. 8-2 Control Registers .. 8-5 Interrupt Latency .. 8-10 INT and External Interrupts .. 8-10 Context Saving During Interrupts .. 8-11 Initialization .. 8-14 Design Tips .. 8-16 Related Application Notes .. 8-17 Revision History .. 8-18 Table of Contents 1997 Microchip Technology v M PAGE SECTION 9.

7 I/O PORTS 9-1 Introduction .. 9-2 PORTA and the TRISA Register .. 9-4 PORTB and the TRISB Register .. 9-6 PORTC and the TRISC Register .. 9-8 PORTD and the TRISD Register .. 9-9 PORTE and the TRISE Register .. 9-10 PORTF and the TRISF Register .. 9-11 PORTG and the TRISG Register .. 9-12 GPIO and the TRISGP Register .. 9-13I/O Programming Considerations .. 9-14 Initialization .. 9-16 Design Tips .. 9-17 Related Application Notes .. 9-19 Revision History .. 9-20 SECTION 10. PARALLEL SLAVE PORT 10-1 Introduction .. 10-2 Control Register .. 10-3 Operation .. 10-4 Operation in Sleep Mode .. 10-5 Effect of a Reset .. 10-5 PSP Waveforms .. 10-5 Design Tips .. 10-6 Related Application Notes .. 10-7 Revision History .. 10-8 Table of Contents DS00097D-page vi 1997 Microchip Technology Inc. M PAGE SECTION 11. TIMER0 11-1 Introduction.

8 11-2 Control Register .. 11-3 Operation .. 11-4 TMR0 Interrupt .. 11-5 Using Timer0 with an External Clock .. 11-6 TMR0 Prescaler .. 11-7 Design Tips .. 11-10 Related Application Notes .. 11-11 Revision History .. 11-12 SECTION 12. TIMER1 12-1 Introduction .. 12-2 Control Register .. 12-3 Timer1 Operation in Timer Mode .. 12-4 Timer1 Operation in Synchronized Counter Mode .. 12-4 Timer1 Operation in Asynchronous Counter Mode .. 12-5 Timer1 Oscillator .. 12-7 Sleep Operation .. 12-9 Resetting Timer1 Using a CCP Trigger Output .. 12-9 Resetting of Timer1 Register Pair (TMR1H:TMR1L) .. 12-9 Timer1 Prescaler .. 12-9 Initialization .. 12-10 Design Tips .. 12-12 Related Application Notes .. 12-13 Revision History .. 12-14 SECTION 13. TIMER2 13-1 Introduction .. 13-2 Control Register .. 13-3 Timer Clock Source .. 13-4 Timer (TMR2) and Period (PR2) Registers.

9 13-4 TMR2 Match Output .. 13-4 Clearing the Timer2 Prescaler and Postscaler .. 13-4 Sleep Operation .. 13-4 Initialization .. 13-5 Design Tips .. 13-6 Related Application Notes .. 13-7 Revision History .. 13-8 SECTION 14. COMPARE/CAPTURE/PWM (CCP) 14-1 Introduction .. 14-2 Control Register .. 14-3 Capture Mode .. 14-4 Compare Mode .. 14-6 PWM Mode .. 14-8 Initialization .. 14-12 Design Tips .. 14-15 Related Application Notes .. 14-17 Revision History .. 14-18 Table of Contents 1997 Microchip Technology vii M PAGE SECTION 15. SYNCHRONOUS SERIAL PORT (SSP) 15-1 Introduction .. 15-2 Control Registers .. 15-3 SPI Mode .. 15-6 SSP I 2 C Operation .. 15-16 Initialization .. 15-26 Design Tips .. 15-28 Related Application Notes .. 15-29 Revision History .. 15-30 SECTION 16. BASIC SYCHRONOUS SERIAL PORT (BSSP) 16-1 Introduction.

10 16-2 Control Registers .. 16-3 SPI Mode .. 16-6 SSP I 2 C Operation .. 16-15 Initialization .. 16-23 Design Tips .. 16-24 Related Application Notes .. 16-25 Revision History .. 16-26 SECTION 17. MASTER SYNCHRONOUS SERIAL PORT (MSSP) 17-1 Introduction .. 17-2 Control Register .. 17-4 SPI Mode .. 17-9 SSP I 2 C Operation .. 17-18 Connection Considerations for I 2 C Bus .. 17-56 Initialization .. 17-57 Design Tips .. 17-58 Related Application Notes .. 17-59 Revision History .. 17-60 SECTION 18. USART 18-1 Introduction .. 18-2 Control Registers .. 18-3 USART Baud Rate Generator (BRG) .. 18-5 USART Asynchronous Mode .. 18-8 USART Synchronous Master Mode .. 18-15 USART Synchronous Slave Mode .. 18-19 Initialization .. 18-21 Design Tips .. 18-22 Related Application Notes .. 18-23 Revision History .. 18-24 Table of Contents DS00097D-page viii 1997 Microchip Technology Inc.