1 U-137. APPLICATION NOTE. Practical Considerations IN high Performance . MOSFET, IGBT and MCT GATE DRIVE CIRCUITS. BILL ANDREYCAK. INTRODUCTION. The switchmode power supply industry's trend towards higher conversion frequencies is justified by the dramatic improvement in obtaining higher power densities. And as these frequencies are pushed towards and beyond one megahertz, the Mosfet transition periods can become a significant portion of the total switching period. Losses associated with the overlap of switch voltage and current not only degrade the overall power supply efficiency, but warrant consideration from both a thermal and packaging standpoint. A/though brief, each of the Mosfet switching transitions can be further reduced if driven from from a high speed, high current totem-pole driver - one designed exclusively for this application. This paper will highlight three such devices; the UC1708 and UC1710 high current Mosfet driver ICs, and the UC1711 high speed driver.
2 Other Mosfet driver ICs and typical application circuits are featured in UNITRODE Application Note U-118. EFFECTIVE GATE CAPACITANCE. The Mosfet input capacitance (Ciss) is frequently adjusting the gate charge numbers accordingly. misused as the load represented by a power mosfet Both turn-on and turn-off trasnsitions are shown with to the gate driver IC. In reality, the effective input the respective drain currents and drain-to-source capacitance of a Mosfet (Ceff) is much higher, and voltages. must be derived from the manufacturers' published total gate charge (Qg) information. Even the speci- fied maximum values of the gate charge parameter TURN-ON WAVEFORMS. do not accurately reflect the driver's instantaneous Gate voltage vs time loads during a given switching transition. Fortunately, FET manufacturers provide a curve for the gate-to- source voltage (Vgs) versus total gate charge in their datasheets. This will be segmented into four time intervals of interest per switching transition.
3 Each of these will be analyzed to determine the effective gate capacitance and driver requirements for optimal Performance . Inadequate gate drive is generally the result TOTAL GATE CHARGE (Qg). First, a typical high power Mosfet Gate Charge versus Gate-to-Source Voltage curve will be ex- amined. An IRFP460 device has been selected and this curve is applicable to most other Fet devices by Figure 1. 3-314. APPLICATION NOTE U-137. INTERVAL t0-t1 INTERVAL t2-t3. The time required to bring the gate voltage from zero Beginning at time t2 the drain-to-source voltage to its threshold Vgs(th) can be expressed as a delay starts to fall which introduces the Miller capaci- time. Both the voltage across the switching device tance effects (Cgd) from the drain to the Mosfet gate. and current through it are uneffected during this The result is the noticeable plateau in the gate interval. voltage waveform from time t2 until t3 while a charge equal to Qgd is admitted. It is here that most drive circuits are taxed to their limits.
4 The interval con- cludes at time t3 when the drain voltage approaches INTERVAL t1-t2 its minimum. This period starts at time t1 when the gate voltage INTERVAL t3-t4. has reached Vgs(th) and drain current begins to flow. Current continues to rise until essentially During this final interval of interest the gate voltage reaching its final value at time t2. While this occurred, rises from the plateau of the prior region up to its final the gate to source voltage had also been increasing. drive voltage. This increasing gate voltage decreases The drain-to-source voltage remains unchanged at Rds(on), the Mosfet drain-to-source resistance. Vds(off). Power in the Mosfet is wasted by the Bringing the gate voltage above 10 to 12 volts, simultaneous overlap of voltage and current. however, has little effect on further reducing Rds(on). SUMMARY OF INTERVAL WAVEFORMS AND DRIVER LIMITATIONS. INTERVAL Vgs(t) ID(t) Vds(t) DRIVER LIMITATIONS. to-t1 0-threshold 0 Vds(off) Slew rate (dv/dt).
5 T1-t2 thrs-plateau rising Vds(off) Slew rate (dv/dt). t2-t3 V(plateau) lon(dc) falling Peak current l(max). t3-t4 rising lon(dc) lon*Rds(t) Peak I & dv/dt TURN-OFF WAVEFORMS INTERVAL t4-t3. Gate voltage vs. time The beginning of the turn-off cycle can be described as a delay from the final drive voltage (Vgs(on)) the the plateau region. Both the drain voltage and cur- rent waveforms remain unchanged while the de- vices effective resistance (Rds(on)) increases as the gate voltage decreases. INTERVAL t3-t2. Once the plateau is reached at time t3, the gate voltage remains constant until time t2. Gate charge due to the Miller effect is being removed, an amount equal to Qgd. The drain voltage rises to its off state amplitude, Vds(off), while the drain current contin- ues to flow and equals l(on). This lossy transition ends at time t2. INTERVAL t2-t1. Once the Miller charge is completely removed, the gate voltage is reduced from the plateau to the threshold voltage causing the drain current to fall from l(on) to zero.
6 Transition power loss ends at time t1 when the gate threshold is crossed. Figure 2. The intervals during turn-off are basically the same INTERVAL t1 -t0. as those described for turn-on, however the se- This brief period is of little interest in the turn-off quence and corresponding waveforms are reversed. sequence since the device is off at time t1. 3-315. APPLICATION NOTE. SUMMARY OF INTERVAL WAVEFORMS AND DRIVER LIMITATIONS. INTERVAL Vgs(t) ID(t) Vds(t) DRIVER LIMITATIONS. t4-t3 falling Ion(dc) Ion Rds(t) Peak I and dv/dt t3-t2 V(plateau) lon(dc) falling Peak Current I (max). t2-t1 Vplat-thrsh falling Vds(off) Slew rate (dv/dt). t1-t0 thrsh-0 0 Vds(off) Slew rate (dv/dt). FET Transition Power Loss Ploss = Vds(off)*l(on)*t(trans)/t(period). During each of the FET turn-on and turn-off se- This relationship displays the need for fast transi- quences power is lost due to the switching device's tions at any switching frequency, and is of significant simultaneous overlap of drain - source voltage and concern at one megaHertz.
7 Minimization of the FET. drain current. Since both the FET voltage and cur- transition power loss can be achieved with high rent are externally controlled by the application, the current drivers. driver IC can only reduce the power losses by making the transition times as brief as possible. GATE CHARGE. Minimization of these losses simply requires a competent driver IC, one able to provide high peak Each division of the transition interval has an asso- currents with high voltage slew rates. ciated gate charge which can be derived from the FET manufacturers datasheets. Since there are A review of the prior transition waveforms indicates three basic shapes to the Vgs curve, the interval that power is lost between the times of t1 and t3. from t0 to t1 can be lumped together with that of the While t2 serves as the pivot point for which waveform t1 to t2 period. For most large FET geometries, the is rising or falling, as the equations show its irrelavent amount of charge in the t0 to - t1 span is negligible in the power loss equation.
8 For the purpose of anyway. This simplification allows an easy calcula- brevity, the waveform of interest can be approxi- tion of the effective gate capacitance for each inter- mated as a triangle while the other waveform is val along with quantifying the peak current required constant. The duration between times t1 and t3 can to traverse in a given amount of time. now be defined as the net transition time, t(tran), with a conversion period of t(period) Charge can be represented as the product of ca- pacitance multiplied by voltage, or current multiplied During the two intervals from t1 to t3: by time. The effective gate capacitance is determined by dividing the required gate charge (Qg) by the * l(on) * Vds(off) * t(2-1) gate voltage during a given interval. Likewise, the Ploss = current necessary to force a transition within a t(period) specified time is obtained by dividing the gate charge by the desired time. * Vds(off) * l(on) *t(3-2). Ploss = Cgs (effective) = delta Qg / delta Vgs t(period).
9 Ig(required) = delta Qg / t(transition). Combining the two equations with t(tran). = t3-1 results in a net loss of: UC1710. The MILLER KILLER . * Vds(off) * l(on) * t(trans). Ploss = high peak gate drive currents are desirable in par- t(period) alleled FET applications, typical of a high power switching section or power factor correction stage. Since these loses are incurred twice percycle, first at Dubbed as the Miller Killer , the UC1710 boasts a turn-on and then again at turn-off, the net result is a guaranteed 6 amp peak output current. This hefty doubling of the power loss. driver current minimizes the FET parasitic Miller . effects which would otherwise result in poor transi- 3-316. APPLICATION NOTE U -137. tion Performance . Higher currents are possible with UC 1708 BLOCK DIAGRAM. this driver, however the limiting factor soon be- comes the parasitic series inductance of the FET. package (15 nH) and the layout interconnection of 20 nH/inch. An RF type arrangement of the PC.
10 Board layout is an absolute MUST to realize this device's full potential. UC 1710 BLOCK DIAGRAM. I. The UC1708 is a unique blend of the high speed attributes of the UC1711 along with the higher peak current capability of the UC1710. This dual noninverting driver accepts positive TTL/CMOS logic from control circuits and provides 3 amp peak out- puts from each totem pole. Propagation delays are under 25 nanoseconds while rise and fall times typically run 35 nanoseconds into nanoFarads. The output stage design is a no float version which incorporates a self biasing The UC1710 has no-load rise and fall times of 20 technique to hold the outputs low during undervoltage nanoseconds (or less) which do not change signifi- lockout, even with Vin removed. cantly with any loads under 3 nanoFarads. It's also specified into a load capacitance of 30 nanoFarads, In the 16 pin DIL package, the device features a roughly equivalent to what is represented by three remote ENABLE and SHUTDOWN function in ad- paralleled size 6 FET devices.