QorIQ LS1046A, LS1026A Data Sheet

1 LS1046 AQorIQ LS1046A, LS1026 AData SheetFeatures LS1046A has four cores and LS1026A has two cores Four 32-bit/64-bit Arm Cortex -v8 A72 CPUs Arranged as a single cluster of four cores sharing asingle 2 MB L2 cache Up to GHz operation Single-threaded cores with 32 KB L1 data cache and48 KB L1 instruction cache Hierarchical interconnect fabric Up to 700 MHz operation One 32-bit/64-bit DDR4 SDRAM memory controllerwith ECC and interleaving support Up to GT/s Data Path Acceleration Architecture (DPAA)incorporating acceleration for the following functions: Packet parsing, classification, and distribution(FMan) Queue management for scheduling, packetsequencing, and congestion management (QMan) Hardware buffer management for buffer allocationand de-allocation (BMan) Cryptography acceleration (SEC) IEEE 1588 support Two RGMII interfaces Eight SerDes lanes for high-speed peripheral interfaces Three PCI Express controllers One Serial ATA (SATA 6 Gbit/s) controller Up to two XFI (10 GbE)

2 Interfaces Up to five SGMII interfaces supporting 1000 Mbps Up to three SGMII interfaces supporting 2500 Mbps Up to one QSGMII interface Supports 10 GBase-KR Supports 1000 Base-KX Additional peripheral interfaces One Quad Serial Peripheral Interface (QSPI)controller One Serial Peripheral Interface (SPI) controller Integrated flash controller (IFC) supporting NANDand NOR flash Three high-speed USB controllers withintegrated PHY One Enhanced Secure Digital Host Controllersupporting SD , eMMC , and eMMC Four I2C controllers Two 16550-compliant DUARTs and six low-powerUARTs (LPUARTs) General purpose IO (GPIO), eight Flextimers One Queue Direct Memory Access Controller(qDMA) One Enhanced Direct Memory Access Controller(eDMA) Global programmable interrupt controller (GIC) Thermal monitoring unit (TMU) 780 FC-PBGA package, 23 mm x 23 mmNXP SemiconductorsDocument Number LS1046 AData Sheet : Technical DataRev.

3 4, 06/2020 NXP reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its of BGA ball layout DC electrical power ramp SDRAM interface, Ethernet management interface, IEEE Flash secure digital host controller (eSDHC).. serial interfaces (HSSI)..1554 Security fuse design platform frequency requirements for DPAA frequency thermal management parameters for the dimensions of the numbering marking ..1919 Revision LS1046A, LS1026A Data Sheet , Rev. 4, 06/20202 NXP Semiconductors1 IntroductionThe LS1046A is a cost-effective, power-efficient, and highly integrated system-on-chip(SoC) design that extends the reach of the NXP value-performance line of QorIQcommunications processors.

4 Featuring power-efficient 64-bit Arm Cortex -A72 coreswith ECC-protected L1 and L2 cache memories for high reliability, running up to LS1046A and LS1026A processors are perfectly suited for a range of embeddedapplications such as enterprise routers and switches, linecard controllers, networkattached storage, security appliances, virtual customer premise equipment (vCPE),service providers gateways, and single board figure shows the block diagram of the Trust ZonePower ManagementIFC, QSPI, SPI 2x DUART64-bitDDR4 Memory ControllerReal Time Debug PerfMonitor4x I2C, GPIO 2 MB L2 - CacheSecure Boot8x FlexTimerSATA 10 GHz SerDes SMMUs3x w/PHY PCIe PCIe PCIe SD/SDIO/eMMCDMA Core ComplexAccelerators and Memory ControlBasic Peripherals, Interconnect, and DebugNetworking Elements 4-Lane 10 GHz SerDes QueueManagerBufferManagerParse, classify,distribute1 GFrame ManagerSecurityEngine(SEC)

5 DPAA Hardware1 1G32 KBD-Cache32 KBI-Cache32 KBD-Cache32 KBI-Cache32 KBD-Cache32 KBI-Cache32 KBD-Cache48 KBI-Cache 1G6x LPUART1G 1 Coherency Fabric Arm Cortex -A7232-bit/64-bit Core1 GFigure 1. LS1046A block diagramIntroductionQorIQ LS1046A, LS1026A Data Sheet , Rev. 4, 06/2020 NXP Semiconductors3 Watchpoint Cross Trigger Trust ZonePower ManagementIFC, QSPI, SPI 2x DUART64-bitDDR4 Memory ControllerReal Time Debug PerfMonitor4x I2C, GPIO 2 MB L2 - CacheSecure Boot8x FlexTimerSATA 10 GHz SerDes SMMUs3x w/PHY PCIe PCIe PCIe SD/SDIO/eMMCDMA Core ComplexAccelerators and Memory ControlBasic Peripherals, Interconnect, and DebugNetworking Elements 4-Lane 10 GHz SerDes QueueManagerBufferManagerParse, classify,distribute1 GFrame ManagerSecurityEngine(SEC)

6 DPAA Hardware1 1G32 KBD-Cache32 KBI-Cache32 KBD-Cache32 KBI-Cache32 KBD-Cache32 KBI-Cache32 KBD-Cache48 KBI-Cache 1G6x LPUART1G 1 Coherency Fabric Arm Cortex -A7232-bit/64-bit Core1 GFigure 2. LS1026A block diagram2 Pin BGA ball layout diagramsThis figure shows the complete view of the LS1046A BGA ball map diagram. Figure 4,Figure 5, Figure 6, and Figure 7 show quadrant assignmentsQorIQ LS1046A, LS1026A Data Sheet , Rev. 4, 06/20204 NXP Semiconductors123456789101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28123456789101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHABCD EFGHJKLMNPRTUVWYAAABACADAEAFAGAHDDRC1 IFCDUARTI2 CeSPIeSDHCI nterruptsBattery Backed TrustTrustSystem ControlASLEEPSYSCLKDDR ClockingRTCD ebugDFTJTAGA nalog SignalsSerdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2EC1EC2 USBDIFF_SYSCLKP owerGroundNo Connects SEE DETAIL ASEE DETAIL BSEE DETAIL CSEE DETAIL

7 DFigure 3. Complete BGA Map for the LS1046 APin assignmentsQorIQ LS1046A, LS1026A Data Sheet , Rev. 4, 06/2020 NXP Semiconductors51234567891011121314123456 7891011121314 ABCDEFGHJKLMNPABCDEFGHJKLMNPIFC_AD00 IFC_AD01 IFC_AD02 IFC_AD03 IFC_AD04 IFC_AD05 IFC_AD06 IFC_AD07 IFC_AD08 IFC_AD09 IFC_AD10 IFC_AD11 IFC_A16 IFC_A17 IFC_A18 IFC_A19 IFC_A20 IFC_A21 IFC_A22 IFC_A23 IFC_A24 IFC_A25 IFC_A26 IFC_A27 IFC_TEUART1_SOUTUART2_SOUTUART1_SINUART2 _SINUART1_RTS_BUART2_RTS_BUART1_CTS_BUAR T2_CTS_BIIC1_SCLIIC1_SDAIIC2_SCLIIC2_SDA SDHC_CMDSDHC_DAT0 SDHC_CLKIRQ00 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 EVT9_BTA_BB_TMP_DETECT_BPORESET_BHRESET_ BRESET_REQ_BASLEEPSYSCLKEVT0_BEVT1_BEVT2 _BEVT3_BEVT4_BTD1_ANODETD1_CATHODEUSB1_D _PUSB1_D_MUSB1_VBUSUSB1_IDUSB1_TX_PUSB1_ TX_MUSB1_RX_PUSB1_RX_MUSB1_RESREFUSB2_D_ PUSB2_D_MUSB2_VBUSUSB2_IDUSB2_TX_PUSB2_T X_MUSB2_RX_PUSB2_RX_MUSB2_RESREFUSB3_D_P USB3_D_MUSB3_VBUSUSB3_IDUSB3_TX_PUSB3_TX _MUSB3_RX_PUSB3_RX_MUSB3_RESREFIIC3_SCLI IC3_SDAIIC4_SCLIIC4_SDAUSB_DRVVBUSUSB_PW RFAULTTH_TPANC_F12NC_K10NC_K11NC_K12NC_K 9NC_L9NC_P5NC_P8 DDRC1 IFCDUARTI2 CeSPIeSDHCI nterruptsBattery Backed TrustTrustSystem ControlASLEEPSYSCLKDDR ClockingRTCD ebugDFTJTAGA nalog SignalsSerdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY

8 3 Ethernet MI 1 Ethernet MI 2EC1EC2 USBDIFF_SYSCLKGND001 GND002 GND004 GND005 GND006 GND007 GND008 GND014 GND015 GND016 GND019 GND020 GND021 GND022 GND023 GND028 GND029 GND030 GND033 GND034 GND035 GND036 GND040 GND041 GND042 GND043 GND044 GND047 GND048 GND049 GND050 GND057 GND058 GND059 GND060 GND061 GND062 GND063 GND067 GND068 GND069 GND070 GND075 GND076 GND077 GND078 GND084 GND085 GND086 GND087 GND093 GND094 GND095 GND096 GND097 GND098 GND099 GND105 GND106 GND107 GND108 OVDD1 DVDD1 DVDD2 PROG_MTRTA_PROG_SFPTH_VDDVDD01 VDD05 VDD06 VDD10 VDD11 VDD12 VDD15 VDD16 VDD17 VDD21 VDD22 VDD23TA_BB_VDDAVDD_CGA1 AVDD_CGA2 AVDD_PLATUSB_HVDD1 USB_HVDD2 USB_SDVDD1 USB_SDVDD2 USB_SVDD1 USB_SVDD2 PowerGroundNo ConnectsFigure 4.

9 Detail APin assignmentsQorIQ LS1046A, LS1026A Data Sheet , Rev. 4, 06/20206 NXP Semiconductors15161718192021222324252627 281516171819202122232425262728 ABCDEFGHJKLMNPABCDEFGHJKLMNPD1_MDQ00D1_M DQ01D1_MDQ02D1_MDQ03D1_MDQ04D1_MDQ05D1_M DQ06D1_MDQ07D1_MDQ08D1_MDQ09D1_MDQ10D1_M DQ11D1_MDQ12D1_MDQ13D1_MDQ14D1_MDQ15D1_M DQ16D1_MDQ17D1_MDQ18D1_MDQ19D1_MDQ20D1_M DQ21D1_MDQ22D1_MDQ23D1_MDQ24D1_MDQ25D1_M DQ26D1_MDQ27D1_MDQ28D1_MDQ29D1_MDQ30D1_M DQ31D1_MECC0D1_MECC1D1_MECC4D1_MECC5D1_M ALERT_BD1_MDM0D1_MDM1D1_MDM2D1_MDM3D1_MD M8D1_MDQS0D1_MDQS1D1_MDQS2D1_MDQS3D1_MDQ S8D1_MDQS0_BD1_MDQS1_BD1_MDQS2_BD1_MDQS3 _BD1_MDQS8_BD1_MBG0D1_MBG1D1_MA01D1_MA02 D1_MA03D1_MA04D1_MA05D1_MA06D1_MA07D1_MA 08D1_MA09D1_MA11D1_MA12D1_MACT_BD1_MCKE0 D1_MCKE1D1_MDIC0 IFC_AD12 IFC_AD13 IFC_AD14 IFC_AD15 IFC_PAR0 IFC_PAR1

10 IFC_CS0_BIFC_CS1_BIFC_CS2_BIFC_CS3_BIFC_ WE0_BIFC_BCTLIFC_NDDQSIFC_AVDIFC_CLEIFC_ OE_BIFC_WP0_BIFC_RB0_BIFC_RB1_BIFC_PERR_ BIFC_CLK0 IFC_CLK1 IFC_NDDDR_CLKIRQ01TA_TMP_DETECT_BDDRCLKR TCCKSTP_OUT_BCLK_OUTSCAN_MODE_BTEST_SEL_ BTCKTDITDOTMSTRST_BD1_TPATBSCAN_EN_BJTAG _BSR_VSELNC_K22NC_L21NC_M20NC_N21NC_P20N C_P21 DDRC1 IFCDUARTI2 CeSPIeSDHCI nterruptsBattery Backed TrustTrustSystem ControlASLEEPSYSCLKDDR ClockingRTCD ebugDFTJTAGA nalog SignalsSerdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2EC1EC2 USBDIFF_SYSCLKGND003 GND009 GND010 GND011 GND012 GND013 GND017 GND018 GND024 GND025 GND026 GND027 GND031 GND032 GND037 GND038 GND039 GND045 GND046 GND051 GND052 GND053 GND054 GND055 GND056 GND064 GND065 GND066 GND071 GND072 GND073 GND074 GND079 GND080 GND081 GND082 GND083 GND088 GND089 GND090 GND091 GND092 GND100 GND101 GND102 GND103 GND104 GND109 GND110 GND111 GND112 SENSEGNDOVDD2 OVDD3 OVDD4 OVDD5G1 VDD01G1 VDD02G1 VDD03G1 VDD04G1 VDD05G1 VDD06G1 VDD07G1 VDD08G1 VDD09G1 VDD10G1 VDD11 VDD02 VDD03 VDD04 VDD07 VDD08 VDD09 VDD13 VDD14 VDD18 VDD19 VDD20 VDD24 VDD25 SENSEVDDP owerGroundNo ConnectsFigure 5.