RI5CY: User Manual - PULP platform

1 ri5cy : user Manual April 2019 Revision Andreas Traber Michael Gautschi Pasquale Davide Schiavone Micrel Lab and Multitherman Lab University of Bologna, Italy Integrated Systems Lab ETH Z rich, Switzerland ri5cy Rev. Page 2 of 57 Copyright 2018 ETH Zurich and University of Bologna. Copyright and related rights are licensed under the Solderpad Hardware License, Version (the License ); you may not use this file except in compliance with the License. You may obtain a copy of the License at Unless required by applicable law or agreed to in writing, software, hardware and materials distributed under this License is distributed on an AS IS BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

2 ri5cy Rev. Page 3 of 57 Document Revisions Rev. Date Author Description Andreas Traber First Draft Andreas Traber Added instruction encoding Michael Gautschi Typos and general corrections Schiavone Removed , and replaced with Schiavone Added register variants of clip, addnorm, and bit manipulation instructions Michael Gautschi Fixed typos, references, foot notes and date style Schiavone Updated to priv spec and new IRQ handling Schiavone General updates Michael Gautschi Extended with optional FP support Schiavone Revised instructions added in Rev. Schiavone Add note in HW Loop A. Ruospo Fixed CSR reset values and general corrections Schiavone Fixed Documentation issue with instruction #29 Schiavone Fixed Documentation issue in Debug Schiavone Fixed Nested Exception Support #40 Schiavone PMP plus priv spec Schiavone New debug.

3 Change HWLoop addresses. ri5cy Rev. Page 4 of 57 Table of Contents 1 Introduction .. 6 Supported Instruction Set .. 6 Optional Floating Point Support .. 7 ASIC Synthesis .. 7 FPGA Synthesis .. 7 Outline .. 7 2 Instruction Fetch .. 8 8 3 Load-Store-Unit (LSU) .. 9 Misaligned Accesses .. 9 9 Physical Memory Protection (PMP) unit .. 11 Post-Incrementing Load and Store Instructions .. 11 4 Multiply-Accumulate .. 12 5 PULP ALU Extensions .. 13 6 Optional private Floating Point Unit (FPU) .. 14 FP 15 Floating-point Performance Counters: .. 16 Some hints on synthesizing the FPU .. 16 7 PULP Hardware Loop Extensions .. 17 CSR Mapping .. 17 8 Pipeline .. 18 9 Register File .. 19 Latch-based Register File .. 19 FPU Register File .. 19 10 Control and Status 20 Machine Status (MSTATUS) .. 20 user Status (USTATUS).

4 20 Machine Trap-Vector Base Address (MTVEC).. 21 user Trap-Vector Base Address (UTVEC) .. 21 Machine Exception PC (MEPC) .. 22 user Exception PC (UEPC) .. 22 Machine Cause (MCAUSE) .. 23 user Cause (UCAUSE) .. 23 Privilege Level .. 23 ri5cy Rev. Page 5 of 57 MHARTID/UHARTID .. 24 24 PMPADDRx .. 24 DCSR .. 24 DPC .. 24 DSCRATCH0/DSCRATCH1 .. 24 11 Performance Counters .. 26 Performance Counter Mode Register (PCMR) .. 27 Performance Counter Event Register (PCER) .. 27 Performance Counter Counter Register (PCCR0-31) .. 29 12 Exceptions and Interrupts .. 31 Interrupts .. 31 Exceptions .. 31 Handling .. 31 13 Debug 33 14 Instruction Set Extensions .. 34 Post-Incrementing Load & Store Instructions .. 34 Encoding .. 40 Hardware Loops .. 38 Operations .. 38 Encoding .. 38 ALU.

5 39 Bit Manipulation Operations .. 39 Bit Manipulation Encoding .. 40 General ALU Operations .. 40 General ALU Encoding .. 42 Immediate Branching Operations .. 44 Immediate Branching Encoding .. 44 Multiply-Accumulate .. 44 MAC Operations .. 44 MAC Encoding .. 53 Vectorial .. 54 Vectorial ALU Operations .. 55 Vectorial ALU 49 Note: Imm6[5:0] is encoded as { Imm6[0], Imm6[5:1] }, LSB at the 25th bit of the instruction .. 54 Vectorial Comparison Operations .. 54 Vectorial Comparison Encoding .. 60 Note: Imm6[5:0] is encoded as { Imm6[0], Imm6[5:1] }, LSB at the 25th bit of the instruction .. 61 ri5cy Rev. Page 6 of 57 1 Introduction ri5cy is a 4-stage in-order 32b RISC-V processor core. The ISA of ri5cy was extended to support multiple additional instructions including hardware loops, post-increment load and store instructions and additional ALU instructions that are not part of the standard RISC-V ISA.

6 Figure 1 shows a block diagram of the core. Figure 1: Block Diagram Supported Instruction Set ri5cy supports the following instructions: Full support for RV32I Base Integer Instruction Set Full support for RV32C Standard Extension for Compressed Instructions Full support for RV32M Integer Multiplication and Division Instruction Set Extension Optional full support for RV32F Single Precision Floating Point Extensions PULP specific extensions o Post-Incrementing load and stores, see Chapter 3 o Multiply-Accumulate extensions, see Chapter 4 o ALU extensions, see Chapter 5 o Hardware Loops, see Chapter 7 ri5cy Rev. Page 7 of 57 Optional Floating Point Support Floating-point support in the form of IEEE-754 single precision can be enabled by setting the parameter FPU of the toplevel file riscv_core to one. This will instantiate the FPU in the execution stage, and also extend the register file to host floating-point operands and extend the ALU to support the floating-point comparisons and classifications.

7 ASIC Synthesis ASIC synthesis is supported for ri5cy . The whole design is completely synchronous and uses positive-edge triggered flip - flops , except for the register file, which can be implemented either with latches or with flip - flops . See Chapter 8 for more details about the register file. The core occupies an area of about 50 kGE when the latch based register file is used. With the FPU, the core area increases to about 90 kGE (30kGE FPU, 10kGE additional register file). FPGA Synthesis FPGA synthesis is supported for ri5cy when the flip -flop based register file is used. Since latches are not well supported on FPGAs, it is crucial to select the flip -flop based register file. Outline This document summarizes all the functionality of the ri5cy core in more detail. First, the instruction and data interfaces are explained in Chapter 2 and 3.

8 The multiplier as well as the ALU are then explained in Chapter 4 and 5. Chapter 7 focuses on the hardware loop extensions and Chapter 9 explains the register file. Control and status registers are explained in Chapter 10 and Chapter 11 gives an overview of all performance counters. Chapter 12 deals with exceptions and interrupts, and Chapter 13 summarizes the accessible debug registers. Finally, Chapter 14 gives an overview of all instruction-extensions, its encodings and meanings. ri5cy Rev. Page 8 of 57 2 Instruction Fetch The instruction fetcher of the core is able to supply one instruction to the ID stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle. The instruction address must be half-word-aligned due to the support of compressed instructions. It is not possible to jump to instruction addresses that have the LSB bit set.

9 For optimal performance and timing closure reasons, a prefetcher is used which fetches instruction from the instruction memory, or instruction cache. There are two prefetch flavors available: 32-Bit word prefetcher. It stores the fetched words in a FIFO with three entries. 128-Bit cache line prefetcher. It stores one 128-bit wide cache line plus 32-bit to allow for cross-cache line misaligned instructions. Table 1 describes the signals that are used to fetch instructions. This interface is a simplified version that is used by the LSU that is described in Chapter 3. The difference is that no writes are possible and thus it needs less signals. Signal Direction Description instr_req_o output Request ready, must stay high until instr_gnt_i is high for one cycle instr_addr_o[31:0] output Address instr_rdata_i[31:0] input Data read from memory instr_rvalid_i input instr_rdata_is holds valid data when instr_rvalid_i is high.

10 This signal will be high for exactly one cycle per request. instr_gnt_i input The other side accepted the request. instr_addr_o may change in the next cycle Table 1: Instruction Fetch Signals Protocol The protocol used to communicate with the instruction cache or the instruction memory is the same as the protocol used by the LSU. See the description of the LSU in Chapter for details about the protocol. ri5cy Rev. Page 9 of 57 3 Load-Store-Unit (LSU) The LSU of the core takes care of accessing the data memory. Load and stores on words (32 bit), half words (16 bit) and bytes (8 bit) are supported. Table 2 describes the signals that are used by the LSU. Signal Direction Description data_req_o output Request ready, must stay high until data_gnt_i is high for one cycle data_addr_o[31:0] output Address data_we_o output Write Enable, high for writes, low for reads.