RM0368 Reference manual - STMicroelectronics

1 December 2018RM0368 Rev 51/847RM0368 Reference manualSTM32F401xB/C and STM32F401xD/E advanced Arm -based 32-bit MCUsIntroductionThis Reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F401xB/C and STM32F401xD/E and STM32F401xD/E are part of the STM32F401xx family of microcontrollers with different memory sizes, packages and ordering information, mechanical and electrical device characteristics refer to the information on the Arm Cortex -M4 with FPU core, refer to the Cortex -M4 with FPU Technical Reference documentsAvailable from STMicroelectronics web site ( ): STM32F401xB/C datasheet STM32F401xD/E datasheet For information on the Arm -M4 core with FPU, refer to the STM32F3xx/F4xxx Cortex -M4 with FPU-M4 programming manual (PM0214).

2 Rev 5 Contents1 Documentation conventions .. of abbreviations for registers .. availability .. 352 Memory and bus architecture .. architecture .. memory bus .. peripheral bus .. bridges (APB) .. organization .. map .. SRAM .. memory overview .. banding .. configuration .. 413 Embedded Flash memory interface .. features .. Flash memory in STM32F401xB/C andSTM32F401xD/E .. interface .. between CPU clock frequency and Flash memory read time . real-time memory accelerator (ART Accelerator ) .. and program operations .. the Flash control register .. parallelism .. 50RM0368 Rev 53 .. bytes .. of user option bytes .. user option bytes .. protection (RDP) .. protections .. code readout protection (PCROP).

3 Programmable bytes .. interface registers .. access control register (FLASH_ACR) .. key register (FLASH_KEYR) .. option key register (FLASH_OPTKEYR) .. status register (FLASH_SR) .. control register (FLASH_CR) .. option control register (FLASH_OPTCR) .. interface register map .. 674 CRC calculation unit .. introduction .. main features .. functional description .. registers .. register (CRC_DR) .. data register (CRC_IDR) .. register (CRC_CR) .. register map .. 705 Power controller (PWR) .. supplies .. A/D converter supply and Reference voltage .. backup domain .. regulator .. supply supervisor .. reset (POR)/power-down reset (PDR) .. reset (BOR) .. 75 ContentsRM03684/847RM0368 Rev voltage detector (PVD).

4 Modes .. down system clocks .. clock gating .. mode .. mode .. mode .. the RTC alternate functions to wake up the device fromthe Stop and Standby modes .. control registers .. power control register (PWR_CR) .. power control/status register (PWR_CSR) .. register map .. 906 Reset and clock control (RCC) for STM32F401xB/Cand STM32F401xD/E .. reset .. reset .. domain reset .. clock .. clock .. configuration .. clock .. clock .. clock (SYSCLK) selection .. security system (CSS) .. clock .. clock .. capability .. clock measurement using TIM5/TIM11 .. registers .. clock control register (RCC_CR) .. PLL configuration register (RCC_PLLCFGR) .. clock configuration register (RCC_CFGR) .. clock interrupt register (RCC_CIR).

5 110RM0368 Rev 55 AHB1 peripheral reset register (RCC_AHB1 RSTR) .. AHB2 peripheral reset register (RCC_AHB2 RSTR) .. APB1 peripheral reset register for (RCC_APB1 RSTR) .. APB2 peripheral reset register (RCC_APB2 RSTR) .. AHB1 peripheral clock enable register (RCC_AHB1 ENR) .. AHB2 peripheral clock enable register (RCC_AHB2 ENR) .. APB1 peripheral clock enable register (RCC_APB1 ENR) .. APB2 peripheral clock enable register(RCC_APB2 ENR) .. AHB1 peripheral clock enable in low power mode register(RCC_AHB1 LPENR) .. AHB2 peripheral clock enable in low power mode register(RCC_AHB2 LPENR) .. APB1 peripheral clock enable in low power mode register(RCC_APB1 LPENR) .. APB2 peripheral clock enabled in low power mode register(RCC_APB2 LPENR) .. Backup domain control register (RCC_BDCR).

6 Clock control & status register (RCC_CSR) .. spread spectrum clock generation register (RCC_SSCGR) .. PLLI2S configuration register (RCC_PLLI2 SCFGR) .. Dedicated Clocks Configuration Register (RCC_DCKCFGR) .. register map .. 1377 System configuration controller (SYSCFG) .. compensation cell .. registers .. memory remap register (SYSCFG_MEMRMP) .. peripheral mode configuration register (SYSCFG_PMC) .. external interrupt configuration register 1(SYSCFG_EXTICR1) .. external interrupt configuration register 2(SYSCFG_EXTICR2) .. external interrupt configuration register 3(SYSCFG_EXTICR3) .. external interrupt configuration register 4(SYSCFG_EXTICR4) .. cell control register (SYSCFG_CMPCR) .. register map .. 145 ContentsRM03686/847RM0368 Rev 58 General-purpose I/Os (GPIO).

7 Introduction .. main features .. functional description .. I/O (GPIO) .. pin multiplexer and mapping .. port control registers .. port data registers .. data bitwise handling .. locking mechanism .. alternate function input/output .. interrupt/wakeup lines .. configuration .. configuration .. function configuration .. configuration .. the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15port pins .. the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins .. of RTC functions .. registers .. port mode register (GPIOx_MODER) (x = and H) .. port output type register (GPIOx_OTYPER) (x = and H) .. port output speed register (GPIOx_OSPEEDR)(x = and H) .. port pull-up/pull-down register (GPIOx_PUPDR)(x = and H) .. port input data register (GPIOx_IDR) (x = and H).

8 Port output data register (GPIOx_ODR) (x = and H) .. port bit set/reset register (GPIOx_BSRR) (x = and H) .. port configuration lock register (GPIOx_LCKR)(x = and H) .. alternate function low register (GPIOx_AFRL) (x = and H) alternate function high register (GPIOx_AFRH)(x = and H) .. register map .. 164RM0368 Rev 57/847RM0368 Contents239 DMA controller (DMA) .. introduction .. main features .. functional description .. description .. transactions .. selection .. streams .. , destination and transfer modes .. incrementation .. mode .. buffer mode .. data width, packing/unpacking, endianess .. and burst transfers .. transfer completion .. transfer suspension .. controller .. of the possible DMA configurations.

9 Configuration procedure .. management .. interrupts .. registers .. low interrupt status register (DMA_LISR) .. high interrupt status register (DMA_HISR) .. low interrupt flag clear register (DMA_LIFCR) .. high interrupt flag clear register (DMA_HIFCR) .. stream x configuration register (DMA_SxCR) (x = ) .. stream x number of data register (DMA_SxNDTR) (x = ) .. stream x peripheral address register (DMA_SxPAR) (x = ) . stream x memory 0 address register (DMA_SxM0AR) (x = ) stream x memory 1 address register (DMA_SxM1AR) (x = ) stream x FIFO control register (DMA_SxFCR) (x = ) .. register map .. 198 ContentsRM03688/847RM0368 Rev 510 Interrupts and events .. vectored interrupt controller (NVIC) .. features .. calibration value register.

10 And exception vectors .. interrupt/event controller (EXTI) .. main features .. block diagram .. event management .. description .. interrupt/event line mapping .. registers .. mask register (EXTI_IMR) .. mask register (EXTI_EMR) .. trigger selection register (EXTI_RTSR) .. trigger selection register (EXTI_FTSR) .. interrupt event register (EXTI_SWIER) .. register (EXTI_PR) .. register map .. 21211 Analog-to-digital converter (ADC) .. introduction .. main features .. functional description .. on-off control .. clock .. selection .. conversion mode .. conversion mode .. diagram .. watchdog .. mode .. channel management .. Discontinuous mode .. alignment .. programmable sampling time.