Second-Generation Digital Signal Processors (Rev. B)

1 TMS320 second GENERATIONDIGITAL Signal PROCESSORSSPRS010B MAY 1987 REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 770011 ADVANCE INFORMATION concerns new products in thesampling or preproduction phase of data and other specifications are subject tochange without 1991, Texas Instruments Incorporated 80-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 4K Words of On-Chip Secure ProgramEPROM (TMS320E25) 4K Words of On-Chip Program ROM(TMS320C25) 128K Words of Data/Program Space 32-Bit ALU/Accumulator 16 16-Bit Multiplier With a 32-Bit Product Block Moves for Data/ProgramManagement Repeat Instructions for Efficient Use ofProgram Space Serial Port for Direct Codec Interface Synchronization Input for SynchronousMultiprocessor Configurations Wait States for Communication to SlowOff-Chip Memories/Peripherals On-Chip Timer for Control Operations Single 5-V Supply Packaging: 68-Pin PGA, PLCC, andCER-QUAD 68-to-28 Pin Conversion Adapter Socket forEPROM Programming Commercial and Military Versions Available NMOS Technology: TMS32020200-ns cycle CMOS Technology: TMS320C25100-ns cycle TMS320E25100-ns cycle TMS320C25-5080-ns cycle data sheet provides complete design documentation for the Second-Generation devices of the TMS320family.

2 This facilitates the selection of the devices best suited for user applications by providing allspecificationsand special features for each TMS320 member. This data sheet is divided into four major sections: architecture,electrical specifications (NMOS and CMOS), timingdiagrams, and mechanical data. In each of these sections,generic information is presented first, followed by specific device information. An index is provided for quickreference to specific information about a GB Package (Top View)IACKMSCCLKOUT1 CLKOUT2 XFHOLDADXFSXX2 CLKINX1 BRD8D9D10D11D12D13D14D15 READYCLKRCLKXSTRBR/WPSISDSVSS10111213141 5161718192021222324252627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 439876543216867666564636261 VSSD7D6D5D4D3D2D1D0 SYNCINT0 INT1 INT2 VCCDRFSRA0605958575655545352515049484746 4544A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15 VSSVCCVCCVCC68-Pin FN and FZ Packages (Top View)

3 ADVANCE INFORMATIONTMS320 second GENERATIONDIGITAL Signal PROCESSORSSPRS010B MAY 1987 REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 770012 PGA AND PLCC/CER-QUAD PIN ASSIGNMENTSFUNCTION PINFUNCTION PINFUNCTION PINFUNCTION PINFUNCTION PINFUNCTION PINA0K1/26A12K8/40D2E1/16D14A5/3 INT2H1/22 VCCH2/23A1K2/28A13L9/41D3D2/15D15B6/2 ISJ11/46 VCCL6/35A2L3/29A14K9/42D4D1/14 DRJ1/24MP/MC A6/1 VSSB1/10A3K3/30A15L10/43D5C2/13 DSK10/45 MSCC10/59 VSSK11/44A4L4/31 BIOB7/68D6C1/12 DXE11/54 PSJ10/47 VSSL2/27A5K4/32 BRG11/50D7B2/11 FSRJ2/25 READY B8/66 XFD11/56A6L5/33 CLKOUT1 C11/58D8A2/9 FSXF10/53 RSA8/65X1G10/51A7K5/34 CLKOUT2 D10/57D9B3/8 HOLDA7/67R/WH11/48X2/CLKIN F11/52A8K6/36 CLKRB9/64D10A3/7 HOLDAE10/55 STRBH10/49A9L7/37 CLKXA9/63D11B4/6 IACKB11/60 SYNCF2/19A10K7/38D0F1/18D12A4/5 INT0G1/20 VCCA10/61A11L8/39D1E2/17D13B5/4 INT1G2/21 VCCB10/62 On the TMS32020, MP/MCmust be connected to DEFINITIONVCCVSSX1X2/CLKINCLKOUT1 CLKOUT2D15-D0A15-A0PS,DS.

4 ISR/WSTRBRSINT2-INT0MP/MCMSCIACKREADYBRX FHOLDHOLDASYNCBIODRCLKRFSRDXCLKXFSXIIOIO OI/O/ZO/ZO/ZO/ZO/ZIIIOOIOOIOIIIIIO/ZII/O /Z5-V supply pinsGround pinsOutput from internal oscillator for crystalInput to internal oscillator from crystal or external clockMaster clock output (crystal or CLKIN frequency/4)A second clock output signal16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O address bus A15 (MSB) through A0 (LSB)Program, data, and I/O space select signalsRead/write signalStrobe signalReset inputExternal user interrupt inputsMicroprocessor/microcomputer mode select pinMicrostate complete signalInterrupt acknowledge signalData ready input. Asserted by external logic when using slower devices to indicate thatthe current bus transactionis request Signal . Asserted when the TMS320C2x requires access to an external global data memory flag output (latched software-programmable Signal )Hold input.

5 When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines inthe high impedance acknowledge signalSynchronization inputBranch control input. Polled by BIOZ data receive inputClock for receive input for serial portFrame synchronization pulse for receive inputSerial data transmit outputClock for transmit output for serial portFrame synchronization pulse for transmit. Configuration as either an input or an output. I/O/Z denotes input/output/high-impedance second GENERATIONDIGITAL Signal PROCESSORSSPRS010B MAY 1987 REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 770013descriptionThe TMS320 family of 16/32-bit single-chip Digital Signal Processors combines the flexibility of a high-speedcontroller with the numerical capability of an array processor , thereby offering an inexpensive alternative tomultichip bit-slice Processors .

6 The highly paralleled architecture and efficient instruction set provide speed andflexibility to produce a MOS microprocessor family thatis capable of executing more than MIPS (millioninstructions per section). The TMS320 family optimizes speed by implementing functions in hardware thatotherprocessors implement through microcode or software. This hardware-intensive approach provides the designengineer with processing power previously unavailable on a single TMS320 family consists of three generations of Digital Signal Processors . The first generation contains theTMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25,which are described in this data TMS320C30 isa floating-pointDSPdevice designed for even higherperformance. Many features are common among the TMS320 Processors . Specific features are added in eachprocessor to provide different cost/performance tradeoffs.

7 Software compatibility is maintained throughout thefamily to protect the user s investment in architecture. Each processor has software and hardware tools tofacilitate rapid TMS32010, the first NMOS Digital Signal processor in the TMS320 family, was introduced in 1983. Itspowerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovativearchitecture have made this high-performance, cost-effective processor the ideal solution to manytelecommunications, computer, commercial, industrial, and military applications. Since that time, theTMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices havebeen added to the first generation of the TMS320 second generation of the TMS320 family (referred to as TMS320C2x) includes four members, theTMS32020, TMS320C25, TMS320C25-50, and TMS320E25.

8 The architecture of these devices is based uponthat of the , processed in NMOS technology, is source-code compatible with he TMS32010 and in manyapplications is capable of two times the throughput of the first- generation devices. Its enhanced instruction set(109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, andhardware timer make the TMS32020 a powerful addition to the TMS320 ,is capable of an instruction cycle time of 100 ns, and ispin-for-pin and object-code compatible with theTMS32020. The TMS320C25 s enhanced feature set greatlyincreases the functionality of the device over theTMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, aneight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, andthe low-power dissipation inherent to the CMOS process.

9 An extended-temperature range version(TMS320C25 GBA) is also a high-speed version of the TMS320C25. It is capable of an instruction cycle time of ,thus,ispin-for-pinand object-code compatible with the identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM isreplaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development andmodification for immediate evaluation of system second GENERATIONDIGITAL Signal PROCESSORSSPRS010B MAY 1987 REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 770014 Key Features: TMS32020 200-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 128K Words of Total Data/ProgramMemory Space Wait States for Communication to Slower Off-ChipMemories Source Code Compatible With the TMS320C1x Single-Cycle Multiply/Accumulate Instructions Repeat Instructions Global Data Memory Interface Block Moves for Data/Program Management Five Auxiliary Registers With DedicatedArithmetic Unit Serial Port for Multiprocessing or Interfacingto Codecs, Serial Analog-to-DigitalConverters, Features.

10 TMS320C25, TMS320C25-50, TMS320E25 80-ns Instruction Cycle Time (TMS320C25-50) 100-ns Instruction Cycle Time (TMS320C25) 4K Words of On-Chip Secure Program EPROM(TMS320E25) 4K Words of On-Chip ProgramROM (TMS320C25) 544 Words of On-Chip RAM 128K Words of Total Program/DataMemory Space Wait States for Communications toSlower Off-Chip Memories Object-Code Compatible With the TMS32020 Source-Code Compatible With TMS320C1x 24 Additional Instructions to SupportAdaptive Filtering, FFTs, andExtended-Precision Arithmetic Block Moves for Data/Program Management Single-Cycle Multiply/Accumulate Instructions Eight Auxiliary Registers With DedicatedArithmetic Unit Bit-Reversed Indexed-Addressing Mode forRadix-2 FFTS Double-Buffered Serial Port On-Chip Clock Generator Single 5-V Supply NMOS Technology 68-Pin Grid Array (PGA) Package On-Chip Clock Generator Single 5-V Supply Internal Security Mechanism (TMS320E25) 68-to-28 Pin Conversion Adapter Socket CMOS Technology 68-Pin Grid Array (PGA) Package(TMS320C25) 68-Lead Plastic Leaded Chip Carrier (PLCC)Package (TMS320C25, TMS320C25-50) 68-Lead CER-QUAD Package (TMS320E25)Multiplier32-BIT ALU/ACCS hiftersTimerInterruptsData (16)Address (16)+5 VGND32-Bit ALU/ACCS hiftersTimerMP/MCData (16)Address (16)+5 VGND4K-WordsROM/EPROMM ultiplier256-WordData/ProgRAM288-WordDat aRAMI nterruptsSerialInterfaceMulti-ProcessorI nterfaceSerialInterfaceMulti-ProcessorIn terface256-WordData/ProgRAM288-WordDataR AMDEVICERAM ROM/EPROM PROG DATATIMERCYCLETIME(ns)TYPPOWER(mW)