Section 15. Synchronous Serial Port (SSP)

1 1997 Microchip Technology Inc. DS31015A page 15-1 M SSP 15 Section 15. Synchronous Serial Port (SSP) HIGHLIGHTS This Section of the manual contains the following major Introduction .. Control Registers .. SPI Mode .. SSP I 2 C Operation .. Initialization .. Design Tips .. Related Application Revision History .. 15-30 Note: Please refer to Appendix or the device data sheet to determine which devicesuse this module. I 2 C is a trademark of Philips Corporation. PICmicro MID-RANGE MCU FAMILY DS31015A-page 15-2 1997 Microchip Technology Inc. Introduction The Synchronous Serial Port (SSP) module is a Serial interface useful for communicating withother peripherals or microcontroller devices. These peripheral devices may be Serial EEPROMs,shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of twomodes: Serial Peripheral Interface (SPI ) Inter-Integrated Circuit (I 2 C )- Slave mode- I/O slope control, and Start and Stop bit detection to ease software implementation of Master and Multi-master modes SPI is a registered trademark of Motorola 2 C is a trademark of Philips Corporation.

2 1997 Microchip Technology 15-3 Section 15. SSP SSP 15 Control Registers Register 15-1: SSPSTAT: Synchronous Serial Port Status Register R/W-0R/W-0R-0R-0R-0R-0R-0R-0 SMPCKED/APSR/WUABFbit 7bit 0bit 7 SMP: SPI data input sample phaseSPI Master Mode1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output timeSPI Slave ModeSMP must be cleared when SPI is used in slave modebit 6 CKE : SPI Clock Edge Select (Figure 15-3, Figure 15-4, and Figure 15-5)CKP = 0 (SSPCON<4>) 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCKCKP = 1 (SSPCON<4>) 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCKbit 5 D/A : Data/Address bit (I 2 C mode only)1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was addressbit 4 P : Stop bit (I 2 C mode only.)

3 This bit is cleared when the SSP module is disabled)1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected lastbit 3 S : Start bit (I 2 C mode only. This bit is cleared when the SSP module is disabled)1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected lastbit 2 R/W : Read/Write bit information (I 2 C mode only)This bit holds the R/W bit information following the last address match. This bit is only valid fromthe address match to the next start bit, stop bit, or not ACK = Read 0 = Writebit 1 UA : Update Address (10-bit I 2 C mode only)1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updatedbit 0 BF : Buffer Full Status bitReceive (SPI and I 2 C modes)1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is emptyTransmit (I 2 C mode only)1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is emptyLegendR = Readable bitW = Writable bitU = Unimplemented bit, read as 0 - n = Value at POR reset PICmicro MID-RANGE MCU FAMILY DS31015A-page 15-4 1997 Microchip Technology Inc.

4 Register 15-2:SSPCON: Synchronous Serial Port Control Register R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0 WCOLSSPOVSSPENCKPSSPM3 SSPM2 SSPM1 SSPM0bit 7bit 0bit 7 WCOL : Write Collision Detect bit1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)0 = No collisionbit 6 SSPOV : Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In caseof overflow, the data in SSPSR is lost and the SSPBUF is no longer updated. Overflow canonly occur in slave mode. The user must read the SSPBUF, even if only transmitting data,to avoid setting overflow. In master mode the overflow bit is not set since each new recep-tion (and transmission) is initiated by writing to the SSPBUF = No overflowIn I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a don t care in transmit mode.

5 SSPOV must be cleared in software in either = No overflowbit 5 SSPEN : Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or SPI mode: 1 = Enables Serial port and configures SCK, SDO, SDI, and SS as the source of the Serial port pins 0 = Disables Serial port and configures these pins as I/O port pinsIn I 2 C mode: 1 = Enables the Serial port and configures the SDA and SCL pins as the source of the Serial port pins 0 = Disables Serial port and configures these pins as I/O port pinsbit 4 CKP : Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low levelIn I 2 C mode: SCK release control1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) 1997 Microchip Technology 15-5 Section 15. SSP SSP 15 bit 3:0 SSPM3:SSPM0 : Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = F OSC /4 0001 = SPI master mode, clock = F OSC /16 0010 = SPI master mode, clock = F OSC /64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin.

6 SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I 2 C slave mode, 7-bit address 0111 = I 2 C slave mode, 10-bit address 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = I 2 C firmware controlled master mode (slave idle) 1100 = Reserved 1101 = Reserved 1110 = I 2 C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I 2 C slave mode, 10-bit address with start and stop bit interrupts enabled LegendR = Readable bitW = Writable bitU = Unimplemented bit, read as 0 - n = Value at POR reset Register 15-2:SSPCON: Synchronous Serial Port Control Register (Cont d) PICmicro MID-RANGE MCU FAMILY DS31015A-page 15-6 1997 Microchip Technology Inc. SPI Mode The SPI mode allows 8-bits of data to be synchronously transmitted and received simulta-neously. All four modes of SPI are supported, as well as Microwire (sample edge) when theSPI is in the master accomplish communication, typically three pins are used: Serial Data Out (SDO) Serial Data In (SDI) Serial Clock (SCK)Additionally a fourth pin may be used when in a slave mode of operation: Slave Select (SS) When initializing the SPI, several options need to be specified.

7 This is done by programming theappropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. Thesecontrol bits allow the following to be specified: Master Mode (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) Data Input Sample Phase Clock Rate (Master mode only) Slave Select Mode (Slave mode only)Figure 15-1 shows the block diagram of the SSP module, when in SPI mode. Figure 15-1:SSP Block Diagram (SPI Mode) ReadWriteInternaldata busSDISDOSSSCKSSPSR regSSPBUF regSSPM3:SSPM0bit0shift clockSSControlEnableEdgeSelectClock SelectTMR2 outputTCYP rescaler4, 16, 64 TRIS bit of SCK pin2 EdgeSelect24 1997 Microchip Technology 15-7 Section 15. SSP SSP 15 The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF).The SSPSR shifts the data in and out of the device, MSb first.

8 The SSPBUF holds the data thatwas written to the SSPSR, until the received data is ready. Once the 8-bits of data have beenreceived, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF(SSPSTAT<0>), and interrupt flag bit, SSPIF, are set. This double buffering of the received data(SSPBUF) allows the next byte to start reception before reading the data that was just write to the SSPBUF register during transmission/reception of data will be ignored, and thewrite collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOLbit so that it can be determined if the following write(s) to the SSPBUF register completed suc-cessfully. When the application software is expecting to receive valid data, the SSPBUF shouldbe read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF(SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmissionis complete).

9 When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if theSPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmis-sion/reception has completed. The SSPBUF must be read and/or written. If the interrupt methodis not going to be used, then software polling can be done to ensure that a write collision doesnot occur. Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. Theshaded instruction is only required if the received data is meaningful (some SPI applications aretransmit only). Example 15-1:Loading the SSPBUF (SSPSR) Register The SSPSR is not directly readable or writable, and can only be accessed from addressing theSSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various statusconditions. BCF STATUS, RP1 ;Specify Bank1 BSF STATUS, RP0 ; LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

10 GOTO LOOP ;No BCF STATUS, RP0 ;Specify Bank0 MOVF SSPBUF, W ;W reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit Microwire is a trademark of National Semiconductor. PICmicro MID-RANGE MCU FAMILY DS31015A-page 15-8 1997 Microchip Technology Inc. SPI I/O To enable the Serial port the SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset orreconfigure SPI mode, clear the SSPEN bit which re-initializes the SSPCON register, and thenset the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as Serial port pins. For thepins to behave as the Serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is: SDI must have the TRIS bit set SDO must have the TRIS bit cleared SCK (Master mode) must have the TRIS bit cleared SCK (Slave mode) must have the TRIS bit set SS must have the TRIS bit setAny Serial port function that is not desired may be overridden by programming the correspondingdata direction (TRIS) register to the opposite value.