Section 3. Data Memory - Microchip Technology

1 2010 Microchip Technology 3-1 data Memory3 Section 3. data MemoryHIGHLIGHTSThis Section of the manual contains the following .. Registers .. Register Descriptions .. Space Address Generator Units (AGUS) .. Addressing .. Addressing .. RAM .. Application Revision History ..3-27dsPIC33F/PIC24H Family Reference ManualDS70202C-page 3-2 2010 Microchip Technology INTRODUCTIONThe dsPIC33F/PIC24H data width is 16 bits. All internal registers and data space Memory areorganized as 16 bits wide. The dsPIC33F/PIC24H features two data spaces. The data spacescan be accessed separately (for some Digital Signal Processing (DSP) instructions), or togetheras one 64-Kbyte linear address range (for microcontroller (MCU) instructions). The data spacesare accessed using two Address Generation Units (AGUs) and separate data 3-1 is an example of a data space Memory map. data Memory addresses between0x0000 and 0x07FF are reserved for the device Special Function Registers (SFRs).

2 The SFRsinclude control bits and status bits for the CPU and peripherals on the RAM begins at address 0x0800 and is split into two blocks, X and Y data space. For datawrites, the X and Y data spaces are always accessed as a single, linear data space. For datareads, the X and Y Memory spaces can be accessed independently or as a single, linear reads for MCU class instructions always access the X and Y data spaces as a singlecombined data space. Dual source operand DSP instructions, such as the MAC instruction,access the X and Y data spaces separately to support simultaneous reads for the two instructions can use any W register as an address pointer for a data read or write data reads, the DSP class of instructions isolates the Y address space from the total dataspace. W10 and W11 are address pointers for reads from the Y data space. The remaining dataspace is referred to as X space, and could more accurately be described as X minus Y and W9 are address pointers for data reads from the X data space in DSP class 3-2 illustrates how the data Memory map functions for both MCU class and DSP classinstructions.

3 Note that the W register number and instruction type determine how address spaceis accessed for data reads. In particular, MCU instructions treat the X and Y Memory as a singlecombined data space. The MCU instructions can use any W register as an address pointer forreads and writes. The DSP instructions that can simultaneously prefetch two data operands, splitthe data Memory into two spaces. Specific W registers must be used for read address pointersin this DSP instructions have the ability to store the accumulator that is not targeted by theinstruction to data Memory . This function is called accumulator write back . W13 must be usedas an address pointer to the combined data Memory space for accumulator write DSP class instructions, W8 and W9 should point to implemented X Memory space for allmemory reads. If W8 or W9 points to Y Memory space, zeros are returned.

4 If W8 or W9 pointsto an unimplemented Memory address, an address error trap is DSP class instructions, W10 and W11 should point to implemented Y Memory space for allmemory reads. If W10 or W11 points to implemented X Memory space, zeros are returned. IfW10 or W11 points to an unimplemented Memory address, an address error trap is to Section 6. Interrupts (DS70184), for more details on address error :This family reference manual Section is meant to serve as a complement to devicedata sheets. Depending on the device variant, this manual Section may not applyto all dsPIC33F/PIC24H consult the note at the beginning of the Memory Organization chapterin the current device data sheet to check whether this document supports thedevice you are data sheets and family reference manual sections are available fordownload from the Microchip Worldwide Web site at: :The data Memory map and the partition between the X and Y data spaces is devicespecific.

5 Refer to the specific dsPIC33F/PIC24H device data sheet for more details. 2010 Microchip Technology 3-3 Section 3. data MemoryData Memory3In addition, some dsPIC33F/PIC24H devices contain DMA and dual-ported SRAM Memory (DPSRAM). Both the CPU and DMA controller can write and read to/from addresses within theDPSRAM without interference, such as CPU stalls, resulting in maximized, real-timeperformance. Refer to Section 22. Direct Memory Access (DMA) (DS70182), for moredetails. Note:The presence and size of DMA RAM is device specific. Refer to the specificdsPIC33F/PIC24H device data sheet for more Family Reference ManualDS70202C-page 3-4 2010 Microchip Technology 3-1:Example data Memory MapNote 1:The size of the X and Y data spaces is device specific. For further details, refer to the specificdevice data sheet. The data space boundaries indicated here are for example purpose :DMA RAM is not available on all devices.

6 Refer to the specific device data sheet, for more :Near data Memory can be accessed directly via file register instructions that encode a 13-bitaddress into the opcode. 4:All data Memory can be accessed indirectly via W registers or directly using the MOV :Upper half of data Memory map can be mapped into a segment of program Memory space forProgram Space Visibility (PSV).0x00000x07FE0x17 FELSbAddress16 bitsLSbMSbMSbAddress0x00010x07FF0x17FF0x FFFFX data RAM 0x80010x8000 Provides ProgramSpace VisibilityUnimplemented0x27FF0x27FE0x280 00x28010x08010x08000x18010x1800 Near DataMemory0x1 FFF0x20010x20000x1 FFEY data RAMX data RAMSFR SpaceDMA RAM 2010 Microchip Technology 3-5 Section 3. data MemoryData Memory3 Figure 3-2: data Spaces for MCU and DSP data MemoryAn 8-Kbyte address space, referred to as near data Memory , is reserved in the data memoryspace between 0x0000 and 0x1 FFF.

7 Near data Memory is directly addressable through a 13-bitabsolute address field within all file register instructions. The Memory regions included in the near data region depend on the amount of data memoryimplemented for each dsPIC33F/PIC24H device variant. At a minimum, the near data regionincludes all the SFRs and some of the X data Memory . For devices that have smaller amountsof data Memory , the near data region can include all of X Memory space and possibly some orall of Y Memory space. Refer to Figure 3-1, for more details. Note:The entire 64K data space can be addressed directly using the MOV to the 16-bit MCU and DSC Programmer s Reference Manual (DS70157),for more details.(Y Space)X SpaceUnusedX SpaceX SpaceUnusedUnusedMCU Class Instructions (Read/Write)Dual Source Operand DSP Instructions (Read)Indirect EA from W10, W11 Indirect EA from W8, W9 Note: data writes for DSP instructions consider the entire data Memory as onecombined space.

8 DSP instructions that perform an accumulator write backuse W13 as an address pointer for writes to the combined data Instructions (Write)Y SpacedsPIC33F/PIC24H Family Reference ManualDS70202C-page 3-6 2010 Microchip Technology CONTROL REGISTERSThis Section outlines the specific functions of each register. MODCON: Modulo and Bit-Reversed Addressing Control Register(1)- Enables or disables the modulo addressing for X AGU and Y AGU- Selects register for Bit-Reversed addressing- Selects register for Modulo addressing XMODSRT: X AGU Modulo Addressing Start Register- Selects Modulo addressing start address for X RAGU and X WAGU XMODEND: X AGU Modulo Addressing End Register- Selects Modulo addressing end address for X RAGU and X WAGU YMODSRT: Y AGU Modulo Addressing Start Register- Selects Modulo addressing start address bits for YGAU YMODEND: Y AGU Modulo Addressing End Register- Selects Modulo addressing end address bits for YGAU XBREV: X Write AGU Bit-Reversal Addressing Control Register- Enables or disables Bit-Reversed addressing for X AGU- Selects buffer for X AGU Bit-Reversed modifier 2010 Microchip Technology 3-7 Section 3.

9 data MemoryData CONTROL REGISTER DESCRIPTIONSThe registers described in this Section control modulo and bit-reversed 3-1:MODCON: Modulo and Bit-Reversed Addressing Control Register(1)R/W-0R/W-0U-0U-0R/W-0R/W-0R/W -0R/W-0 XMODENYMODEN BWM<3:0>bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W- 0 YWM<3:0>XWM<3:0>bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15 XMODEN: X RAGU and X WAGU Modulo Addressing Enable bit1 = X AGU modulo addressing enabled0 = X AGU modulo addressing disabledbit 14 YMODEN: Y AGU Modulo Addressing Enable bit1 = Y AGU modulo addressing enabled0 = Y AGU modulo addressing disabledbit 13-12 Unimplemented: Read as 0 bit 11-8 BWM<3:0>: X WAGU Register Select for Bit-Reversed Addressing bits1111 = Bit-reversed addressing disabled1110 = W14 selected for bit-reversed addressing1101 = W13 selected for bit-reversed addressing 0000 = W0 selected for bit-reversed addressingbit 7-4 YWM<3:0>: Y AGU W Register Select for Modulo Addressing bits1111 = Modulo addressing disabled1010 = W10 selected for modulo addressing1011 = W11 selected for modulo addressingAll other settings of the YWM<3:0> control bits are reserved and should not be 3-0 XWM<3:0>: X RAGU and X WAGU W Register Select for Modulo Addressing bits1111 = Modulo addressing disabled1110 = W14 selected for modulo addressing 0000 = W0 selected for modulo addressingNote 1:A write to the MODCON register should not be followed by an instruction that performs an indirect readoperation using a W register.

10 Unexpected results may occur. Some instructions perform an implicit indirectread. These are: POP, RETURN, RETFIE, RETLW and Family Reference ManualDS70202C-page 3-8 2010 Microchip Technology 3-2:XMODSRT: X AGU Modulo Addressing Start RegisterR/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/ W-0R/W-0XS<15:8>bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R-0X S<7:1>0bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15-1XS<15:1>: X RAGU and X WAGU Modulo Addressing Start Address bitsbit 0 Unimplemented: Read as 0 Register 3-3:XMODEND: X AGU Modulo Addressing End RegisterR/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/ W-0R/W-0XE<15:8>bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R-1X E<7:1>1bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15-1XE<15:1>.