Section 64. Capture/Compare/PWM/Timer (MCCP …

1 2013 Microchip Technology 64-1 MCCP andSCCP64 Section 64. Capture/Compare/PWM/Timer (MCCP and SCCP)HIGHLIGHTSThis Section of the manual contains the following major Introduction .. Registers .. Time Base Generator .. Module Sync Outputs .. Sync and Triggered Operation .. timer Modes .. Output compare and PWM Modes .. Input capture Operation During Sleep and Idle Modes .. Effects of a Reset .. Register Maps .. Related Application Revision History .. 64-62 PIC24F Family Reference ManualDS33035A-page 64-2 2013 Microchip Technology INTRODUCTIONS elect PIC24F family devices include one or more Capture/Compare/PWM/Timer (CCP) modules are similar to the multi-purpose timer modules found on many other 16-bit micro-controllers. They also provide the functionality of the comparable Input capture , Output Compareand General Purpose timer peripherals found in all earlier PIC24F modules can operate in one of three major modes: General Purpose timer Input capture Output compare /PWMT here are two different forms of the module, distinguished by the number of PWM outputs thatthe module can generate.

2 Single output modules (SCCPs) provide only one PWM output modules (MCCPs) can provide up to six outputs and an extended range of outputcontrol features, depending on the pin count of the particular modules (SCCP and MCCP) include these features. User-selectable clock inputs, including system clock and external clock input pins Input clock prescaler for time base Output postscaler for module interrupt events or triggers Synchronization output signal for coordinating other MCCP/SCCP modules with user-configurable alternate and auxiliary source options Fully asynchronous operation in all modes and in low-power operation Special output trigger for A/D conversions 16-Bit and 32-Bit General Purpose timer modes with optional gated operation for simple time measurements capture Modes:- Backward compatible with previous Input capture peripherals of the PIC24F family- 16-bit or 32-bit capture of time base on external event- Up to four-level deep FIFO capture buffer- capture source input multiplexer- Gated capture operation to reduce noise-induced false captures Output compare /PWM Modes- Backward compatible with previous Output compare peripherals of the PIC24F family- Single Edge and Dual Edge compare modes- Center-Aligned compare mode- Variable Frequency Pulse mode- External Input modeMCCP modules also include these extended PWM features: Single Output Steerable mode Brush DC Motor (Forward and Reverse) modes Half-Bridge with Dead-Time Delay Push-Pull PWM mode Output Scan mode Auto-shutdown with programmable source and shutdown state Programmable output polarityThe SCCP and MCCP modules can be operated only in one of the three major modes ( capture , compare or timer ) at any time.

3 The other modes are not available unless the module conceptual block diagram for the module is shown in Figure 64-1. All three modes use the TimeBase Generator and the common timer register pair (CCPxTMRH/L). Other shared hardwarecomponents, such as comparators and buffer registers, are activated and used as a particularmode requires. 2013 Microchip Technology 64-3 Section 64. Capture/Compare/PWM/Timer (MCCP and SCCP)MCCP andSCCP64 Figure 64-1:MCCP/SCCP Conceptual Block REGISTERSEach MCCP/SCCP module has up to seven control and status registers: CCPxCON1L (Register 64-1) controls many of the features common to all modes, including input clock selection, time base prescaling and timer synchronization. The module is also enabled and the operational mode is selected from this register. CCPxCON1H (Register 64-2) controls interrupt generation, Trigger mode operations and postscaler selection for all modes. CCPxCON2L (Register 64-3) controls auto-shutdown and restart operation, primarily for PWM operations.

4 CCPxCON2H (Register 64-4) configures other Input capture and Output compare features, and configures auxiliary output operation. CCPxCON3L (Register 64-5) controls multiple output PWM dead time; it is not available on SCCP modules. CCPxCON3H (Register 64-6) controls the output of the Output compare and PWM modes, and configures the PWM Output mode for MCCP modules. CCPxSTATL (Register 64-7) contains read-only status bits showing the state of module module also includes eight buffer/counter registers that serve as timer Value registers ordata holding buffers: CCPxTMRH and CCPxTMRL are the 32-Bit timer /Counter register pair CCPxPRH and CCPxPRL are the 32-Bit timer Period register pair CCPxRA is the 16-bit primary data buffer for Output compare operations CCPxRB is the 16-bit secondary data buffer for Output compare operations CCPxBUFH and CCPxBUFL are the 32-Bit Buffer register pair, which are used in Input capture FIFO operationsTime BaseGeneratorClockSourcesInput CaptureOutput compare /PWMTMR32 CCSELMOD<3:0>Sync andGatingSources16/32-BitAuxiliary OutputCCPxIFCCTxIFExternalCaptureCompare /PWMO utput(s)OCFA/OCFBT imerCCP Sync OutSpecial Event Trigger Out (A/D)InputCCPxTMRH/LPIC24F Family Reference ManualDS33035A-page 64-4 2013 Microchip Technology Inc.

5 Register 64-1:CCPxCON1L: capture / compare /PWMx Control 1 Low RegisterR/W-0U-0R/W-0R/W-0R/W-0R/W-0R/W- 0R/W-0 CCPON CCPSIDLCCPSLPTMRSYNCCLKSEL2(1)CLKSEL1(1) CLKSEL0(1)bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W- 0 TMRPS1 TMRPS0 TMR32 CCSELMOD3 MOD2 MOD1 MOD0bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15 CCPON: CCPx Module Enable1 = Module is enabled with operating mode specified by MOD<3:0>0 = Module is disabledbit 14 Unimplemented: Read as 0 bit 13 CCPSIDL: CCPx Stop in Idle Mode Bit1 = Discontinues module operation when device enters Idle mode0 = Continues module operation in Idle modebit 12 CCPSLP: CCPx Sleep Mode Enable bit1 = Module continues to operate in Sleep modes0 = Module does not operate in Sleep modesbit 11 TMRSYNC: Time Base Clock Synchronization bit1 = Module time base clock is synchronized to internal system clocks; timing restrictions apply0 = Module time base clock is not synchronized to internal system clocksbit 10-8 CLKSEL<2:0>: CCPx Time Base Clock Select bits(1)111 = Clock 7110 = Clock 6101 = Clock 5100 = Clock 4011 = Clock 3010 = Clock 2001 = Clock 1000 = System Clock (TCY)bit 7-6 TMRPS<1:0>: CCPx Time Base Prescale Select bits11 = 1:64 Prescaler10 = 1:16 Prescaler01 = 1:4 Prescaler00 = 1:1 Prescalerbit 5 TMR32: 32-Bit Time Base Select bit1 = 32-bit time base for timer , single edge Output compare or Input capture function0 = 16-bit time base for timer , single edge Output compare or Input capture functionbit 4 CCSEL: capture / compare Mode Select bit1 = Input capture mode0 = Output compare /PWM or timer mode (exact function selected by MOD<3:0> bits)Note 1:Refer to the device data sheet for available clock sources for a specific device family.

6 2013 Microchip Technology 64-5 Section 64. Capture/Compare/PWM/Timer (MCCP and SCCP)MCCP andSCCP64bit 3-0 MOD<3:0>: CCPx Mode Select bits CCSEL = 1 (Input capture modes):1xxx = Reserved011x = Reserved0101 = capture every 16th rising edge0100 = capture every 4th rising edge0011 = capture every rising and falling edge0010 = capture every falling edge0001 = capture every rising edge0000 = capture every rising and falling edge (Edge Detect mode)CCSEL = 0 (Output compare modes):1111 = External Input mode: pulse generator is disabled, source is selected by ICS<2:0>1110 = Reserved110x = Reserved10xx = Reserved0111 = Variable Frequency Pulse mode0110 = Center-Aligned Pulse compare mode, buffered0101 = Dual Edge compare mode, buffered0100 = Dual Edge compare mode0011 = 16-Bit/32-Bit Single Edge mode: toggle output on compare match0010 = 16-Bit/32-Bit Single Edge mode: drive output low on compare match0001 = 16-Bit/32-Bit Single Edge mode: drive output high on compare match0000 = 16-Bit/32-Bit timer mode.

7 Output functions are disabledRegister 64-1:CCPxCON1L: capture / compare /PWMx Control 1 Low Register (Continued)Note 1:Refer to the device data sheet for available clock sources for a specific device Family Reference ManualDS33035A-page 64-6 2013 Microchip Technology Inc. Register 64-2:CCPxCON1H: capture / compare /PWMx Control 1 High RegisterR/W-0R/W-0U-0U-0R/W-0R/W-0R/W-0R /W-0 OPSSRC(1)RTRGEN(2) OPS3(3)OPS2(3)OPS1(3)OPS0(3)bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W- 0 TRIGENONESHOTALTSYNC(3)SYNC4(4)SYNC3(4)S YNC2(4)SYNC1(4)SYNC0(4)bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15 OPSSRC: Output Postscaler Source Select bit(1)1 = Output postscaler scales Special Event Trigger output events0 = Output postscaler scales timer interrupt eventsbit 14 RTRGEN: Retrigger Enable bit(2)1 = Time base can be retriggered when CCPTRIG = 10 = Time base may not be retriggered when CCPTRIG = 1bit 13-12 Unimplemented: Read as 0 bit 11-8 OPS<3:0>: CCPx Interrupt Output Postscale Select bits(3)1111 = Interrupt every 16th time base period match1110 = Interrupt every 15th time base period match.

8 0100 = Interrupt every 5th time base period match0011 = Interrupt every 4th time base period match or 4th input capture event0010 = Interrupt every 3rd time base period match or 3rd input capture event0001 = Interrupt every 2nd time base period match or 2nd input capture event0000 = Interrupt after each time base period match or input capture eventbit 7 TRIGEN: CCPx Triggered Enable bit1 = Triggered operation of timer is enabled0 = Triggered operation of timer is disabledbit 6 ONESHOT: One-Shot Mode Enable bit1 = One-Shot Triggered mode is enabled; trigger duration is set by OSCNT<2:0>0 = One-Shot Triggered mode is disabledbit 5 ALTSYNC: CCPx Clock Select bits(3)1 = An alternate signal is used as the module synchronization output signal 0 = The module synchronization output signal is the Time Base Reset/Rollover eventbit 4-0 SYNC<4:0>: CCPx Synchronization Source Select bits(4)11111 = timer is in the Free-Running mode and rolls over at FFFFh (period register is ignored)11110 = timer is synchronized to Source #30.

9 00001 = Time base is synchronized to Source #100000 = No external synchronization; timer rolls over at FFFFh or matches with period registerNote 1:Control bit has no function in Input capture :Control bit has no function when TRIGEN = :Values greater than 0011 will cause a FIFO buffer overflow in Input capture :Refer to the device sheet for Sync sources for a specific device family. 2013 Microchip Technology 64-7 Section 64. Capture/Compare/PWM/Timer (MCCP and SCCP)MCCP andSCCP64 Register 64-3:CCPxCON2L: capture / compare /PWMx Control 2 Low RegisterR/W-0R/W-0U-0R/W-0U-0U-0U-0U-0 PWMRSENASDGM SSDG bit 15bit 8R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W- 0 ASDG7(1)ASDG6(1)ASDG5(1)ASDG4(1)ASDG3(1) ASDG2(1)ASDG1(1)ASDG0(1)bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15 PWMRSEN: CCPx PWM Restart Enable bit1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown inputhas ended0 = ASEVT must be cleared in software to resume PWM activity on output pinsbit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit1 = Waits until next Time Base Reset or rollover for shutdown to occur0 = Shutdown event occurs immediately bit 13 Unimplemented: Read as 0 bit 12 SSDG.

10 CCPx Software Shutdown/Gate Control bit1 = Manually forces auto-shutdown, timer clock gate or Input capture signal gate event (setting ofASDGM bit still applies)0 = Normal module operationbit 11-8 Unimplemented: Read as 0 bit 7-0 ASDG<7:0>: CCPx Auto-Shutdown/Gating Source Enable bits(1)1 = Auto-Shutdown/Gating Source n is enabled0 = Auto-Shutdown/Gating Source n is disabledNote 1:Refer to the device data sheet for the specific gating sources implemented for a device Family Reference ManualDS33035A-page 64-8 2013 Microchip Technology Inc. Register 64-4:CCPxCON2H: capture / compare /PWMx Control 2 High RegisterR/W-0U-0R/W-0R/W-0R/W-0R/W-0R/W- 0R/W-1 OENSYNC OCFEN(1)OCEEN(1)OCDEN(1)OCCEN(1)OCBEN(1) OCAENbit 15bit 8R/W-0R/W-0U-0R/W-0R/W-0R/W-0R/W-0R/W-0 ICGSM1 ICGSM0 AUXOUT1(2)AUXOUT0(2)ICS2(3)ICS1(3)ICS0(3 )bit 7bit 0 Legend:R = Readable bitW = Writable bitU = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is clearedx = Bit is unknownbit 15 OENSYNC: Output Enable Synchronization bit1 = Update by output enable bits occurs on the next Time Base Reset or rollover0 = Update by output enable bits occurs immediatelybit 14 Unimplemented: Read as 0 bit 13-8OC<F:A>EN: Output Enable/Steering Control bits(1)1 = OCx pin is controlled by the CCPx module and produces an Output compare or PWM signal0 = OCx pin is not controlled by the CCPx module.