SRAM Nonvolatile Controller Unit - TI.com

1 Features Power monitoring and switchingfor 3-volt battery-backup applica-tions Write-protect control 3-volt primary cell inputs Less than 10ns chip-enablepropagation delay 5% or 10% supply operationGeneral DescriptionThe CMOS bq2201 SRAM NonvolatileController Unit provides all necessaryfunctions for converting a standardCMOS SRAM into nonvolatileread/write precision comparator monitors the5V VCCinput for an out-of-tolerancecondition. When out of tolerance isdetected, a conditioned chip-enableoutput is forced inactive to write-protect any standard CMOS a power failure, the externalSRAM is switched from the VCCsupply to one of two 3V backup sup-plies. On a subsequent power-up, theSRAM is write-protected until apower-valid condition bq2201 is footprint- and timing-compatible with industry stan-dardswith the added benefit of achip-enablepropagation delay ofless than Nonvolatile Controller Unitbq2201 Oct.

2 1998 DPin NamesVOUTS upply outputBC1 BC23-volt primary backup cell inputsTHST hreshold select inputCEchip-enable active low inputCECONC onditioned chip-enable outputVCC+5-volt supply inputVSSG roundNCNo ConnectFunctional DescriptionPin ConnectionsAn external CMOS static RAM can be battery-backedusing the VOUTand the conditioned chip-enable outputpin from the bq2201. As VCCslews down during a powerfailure, the conditioned chip-enable output CECON isforced inactive independent of the chip-enable input activity unconditionally write-protects externalSRAM as VCCfalls to an out-of-tolerance threshold selected by the threshold select input pin, THS is tied to VSS, power-fail detection occurs at for 5% supply operation. If THS is tied to VCC,power-fail detection occurs at typical for 10% sup-ply operation. The THS pin must be tied to VSSor VCCforproper a memory access is in process during power-fail detec-tion, that memory cycle continues to completion before thememory is write-protected.

3 If the memory cycle is not ter-minated within time tWPT, the CECON output is uncondi-tionally driven high, write-protecting the 8-Pin Narrow DIP or SOIC234 8765 VCCBC1 CECONCE SOIC234 5678161514131211109 NCVCCNCBC1 NCCECONNCCENCVOUTNCBC2 NCTHSNCVSSAs the supply continues to fall past VPFD, an internalswitching device forces VOUTto one of the two externalbackup energy sources. CECONis held high by the VOUT energy power-up, VOUTis switched back to the VCCsup-ply as VCCrises above the backup cell input voltagesourcing VOUT. The CECON output is held inactive fortime tCER(120 ms maximum) after the supply hasreached VPFD, independent of the CEinput, to allow forprocessor power-valid operation, the CEinput is fedthrough to the CECON output with a propagation delayof less than 10ns. Nonvolatility is achieved by hardwarehookup, as shown in Figure Cell Inputs BC1,BC2 Two primary backup energy source inputs are providedon the bq2201.

4 The BC1and BC2inputs accept a 3V pri-mary battery, typically some type of lithium no primary cell is to be used on either BC1or BC2, theunused input should be tied to both inputs are used, during power failure the VOUT output is fed only by BC1as long as it is greater If the voltage at BC1falls below , an internalisolation switch automatically switches VOUT from BC1to prevent battery drain when there is no valid data toretain, VOUTand CECONare internally isolated fromBC1and BC2by either of the following:nInitial connection of a battery to BC1or BC2,ornPresentation of an isolation signal on valid isolation signal requires CElow as VCCcrossesboth VPFDand VSOduring a power-down. See Figure these two points in time, CEmust be broughtto the point of ( to )*VCCand held for at least700ns. The isolation signal is invalid if *VCCat any point between VCCcrossing appropriate battery is connected to VOUTand CECON immediately on subsequent application and removal of Address Decoder3 VPrimaryCell3 VPrimaryCellFigure 1.

5 Hardware Hookup (5% Supply Operation)Oct. 1998 VCC700nsFigure 2. Battery Isolation Signalbq22013 Absolute Maximum RatingsSymbolParameterValueUnitCondition sVCCDC voltage applied on VCCrelative to to voltage applied on any pin excluding VCCrelative to to VCC+ temperature0 to +70 CCommercial-40 to +85 CIndustrial N TSTGS torage temperature-55 to +125 CTBIAST emperature under bias-40 to +85 CTSOLDERS oldering temperature260 CFor 10 secondsIOUTVOUT current200mANote:Permanent device damage may occur ifAbsolute Maximum Ratingsare exceeded. Functional opera-tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-sure to conditions beyond the operational limits for extended periods of time may affect device DC Operating Conditions(TA=TOPR)SymbolParameterMinimu mTypicalMaximumUnitNotesVCCS upply = = VCCVSSS upply voltage000 VVILI nput low high + ,VBC2 Backup cell +.

6 Typical values indicate operation at TA= 25 C, VCC= 5V or 1998 Dbq22014DC Electrical Characteristics(TA=TOPR,VCC= 5V 10%)SymbolParameterMinimumTypicalMaximum UnitConditions/NotesILII nput leakage current-- 1 AVIN=VSSto VCCVOHO utput high , BC supplyVBC- >VCC,IOH= -10 AVOLO utput low supply current-35mANoload on VOUTand detect = = VCCVSOS upply switch-over voltage-VBC-VICCDRData-retention modecurrent--100nAVOUT data-retention currentto additional memory not >VBC,IOUT= 100mAVCC- >VBC,IOUT= 160mAVOUT2 VOUT voltageVBC- <VBC,IOUT= 100 AVBCA ctive backup cellvoltage-VBC2-VVBC1< > >VCC- AVOUT>VBC- :Typical values indicate operation at TA= 25 C, VCC= 5V or 1998 Dbq22015AC Test ConditionsParameterTest ConditionsInput pulse levels0V to rise and fall times5nsInput and output timing reference (unless otherwise specified)Output load (including scope and jig)See Figure Figure 3.

7 Output LoadCapacitance(TA= 25 C, F = 1 MHz, VCC= )SymbolParameterMinimumTypicalMaximumUni tConditionsCINI nput capacitance--8pFInput voltage = 0 VCOUTO utput capacitance--10pFOutput voltage = 0 VNote:This parameter is sampled and not 100% 1998 TimingPower-Fail Control(TA = TOPR)SymbolParameterMinimumTypicalMaximu mUnitNotestPFVCC slew, to stFSVCC slew, to VSO10-- stPUVCC slew, to stCEDChip-enable propagationdelay-710nstCERChip-enable recovery4080120msTime during which SRAM iswrite-protected after VCCpasses VPFDon time40100150 sDelay after VCCslews downpast VPFD before SRAM :Typical values indicate operation at TA= 25 : Negative undershoots below the absolute maximum rating of in battery-backup modemay affect data 1998 Dbq22017 Oct. 1998 Timingbq22018 Oct. 1998 D8-Pin SOIC Narrow (SN) dimensions are in SOIC Narrow (SN)8-Pin DIP Narrow (PN) dimensions are in DIP Narrow (PN)bq22019bq2201 Oct.

8 1998 DS: 16-Pin S(SOIC) dimensions are in 1998 DData Sheet Revision HistoryChange of Change1 Added industrial temperature range21, 3, 410% supply operationWas: THS tied to VOUTIs: THS tied to VCC31, 9, 11 Added 16-pin package optionNote:Change 1 = Sept. 1991 B changes from Sept. 1990 2 = Aug. 1997 C changes from Sept. 1991 3 = Oct. 1998 D changes from Aug. 1997 Informationbq2201 Package Option:PN = 8-pin narrow plastic DIPSN = 8-pin narrow SOICS = 16-pin SOICD evice:bq2201 Nonvolatile SRAM ControllerTemperature Range:blank = Commercial (0 to +70 C)N = Industrial (-40 to +85 C)bq2201 Oct. 1998 DPACKAGE OPTION 1 PACKAGING INFORMATIONO rderable DeviceStatus(1)Package TypePackageDrawingPinsPackageQtyEco Plan(2)Lead finish/Ball material(6)MSL Peak Temp(3)Op Temp ( C)Device Marking(4/5)SamplesBQ2201SN-NACTIVESOICD 875 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 852201-NBQ2201SN-NTRACTIVESOICD82500 RoHS & GreenNIPDAUL evel-1-260C-UNLIM-40 to 852201-N (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new : TI has announced that the device will be discontinued, and a lifetime-buy period is in : Not recommended for new designs.

9 Device is in production to support existing customers, but TI does not recommend using this part in a new : Device has been announced but is not in production. Samples may or may not be : TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS : TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold.

10 Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.