STM8L051F3 - st.com

1 This is information on a product in full production. September 2018DS9178 Rev 41/96 STM8L051F38-bit ultra-low-power MCU, 8-Kbyte Flash memory, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADCD atasheet - production dataFeatures Operating conditions Operating power supply: V to V Temperature range: 40 C to 85 C Low-power features 5 low-power modes: Wait, Low-power run ( A), Low-power wait (3 A), Active-halt with RTC ( A), Halt (350 nA) Ultra-low leakage per I/O: 50 nA Fast wakeup from Halt: 5 s Advanced STM8 core Harvard architecture and 3-stage pipeline Max freq: 16 MHz, 16 CISC MIPS peak Up to 40 external interrupt sources Reset and supply management Low power, ultra-safe BOR reset with 5 selectable thresholds Ultra-low power POR/PDR Programmable voltage detector (PVD) Clock management 32 kHz and 1 to 16 MHz crystal oscillators Internal 16 MHz factory-trimmed RC Internal 38 kHz low consumption RC Clock security system Low-power RTC BCD calendar with alarm interrupt Digital calibration with +/- ppm accuracy LSE security system Auto-wakeup from Halt w/ periodic interrupt Memories 8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC Flexible write and read protection modes 1 Kbyte of RAM DMA 4 channels supporting ADC, SPI, I2C, USART, timers 1 channel for memory-to-memory 12-bit ADC up to 1 Msps/10 channels Internal reference voltage Timers Two 16-bit timers with 2 channels (used as IC, OC, PWM)

2 , quadrature encoder One 8-bit timer with 7-bit prescaler 2 watchdogs: 1 Window, 1 Independent Beeper timer with 1, 2 or 4 kHz frequencies Communication interfaces Synchronous serial interface (SPI) Fast I2C 400 kHz SMBus and PMBus USART Up to 18 I/Os, all mappable on interrupt vectors Development support Fast on-chip programming and non-intrusive debugging with SWIM Bootloader using USART TSSOP20 ( mm or 169 mils width) Rev 4 Contents1 Introduction .. 82 Description .. overview .. continuum ..113 Functional overview .. modes .. processing unit STM8 .. STM8 Core .. controller .. and supply management .. supply scheme .. supply supervisor .. regulator .. management .. power real-time clock .. converter .. configuration controller and routing interface .. general purpose timers (TIM2, TIM3) .. basic timer (TIM4) .. timers .. watchdog timer .. watchdog timer.

3 Interfaces .. (IR) interface .. 21DS9178 Rev 43 support .. 214 Pin description .. configuration options .. 255 Memory and register map .. mapping .. map .. 276 Interrupt vector mapping .. 407 Option bytes .. 428 Electrical parameters .. conditions .. and maximum values .. values .. curves .. capacitor .. input voltage .. maximum ratings .. conditions .. operating conditions .. reset and power control block characteristics .. current characteristics .. and timing characteristics .. characteristics .. current injection characteristics .. port pin characteristics .. interfaces .. reference voltage .. ADC1 characteristics .. characteristics .. 859 Package characteristics .. mechanical data .. 89 ContentsSTM8L051F34/96DS9178 Rev package information .. characteristics .. 9210 Ordering information .. 9311 Revision history .. 94DS9178 Rev 45/96 STM8L051F3 List of tables6 List of tablesTable features and peripheral counts.

4 10 Table feature comparison .. 19 Table for Table 4.. 23 Table pin description .. 24 Table and RAM boundary addresses .. 27 Table port hardware register map .. 27 Table hardware register map .. 28 Table module/interrupt controller registers .. 38 Table mapping .. 40 Table byte addresses .. 42 Table byte description .. 43 Table characteristics .. 46 Table characteristics .. 46 Table characteristics.. 47 Table operating conditions .. 48 Table reset and power control block characteristics.. 49 Table current consumption in Run mode .. 51 Table current consumption in Wait mode .. 53 Table current consumption and timing in Low power run mode at VDD = V to V .. 55 Table current consumption in Low power wait mode at VDD = V to V .. 56 Table current consumption and timing in Active-halt mode at VDD = V to V.. 57 Table current consumption in Active-halt mode, RTC clocked by LSE external crystal.

5 57 Table current consumption and timing in Halt mode at VDD = to V .. 58 Table current consumption .. 59 Table consumption under external reset .. 60 Table external clock characteristics .. 60 Table external clock characteristics .. 60 Table oscillator characteristics .. 61 Table oscillator characteristics .. 62 Table oscillator characteristics.. 63 Table oscillator characteristics .. 64 Table and hardware registers .. 65 Table program and data EEPROM memory .. 65 Table current injection susceptibility .. 66 Table static characteristics .. 67 Table driving current (high sink ports).. 70 Table driving current (true open drain ports).. 70 Table driving current (PA0 with high sink LED driver capability).. 70 Table pin characteristics .. 72 Table characteristics .. 74 Table characteristics .. 77 Table voltage characteristics.. 79 Table characteristics .. 80 Table accuracy with VDDA = V to V.

6 82 Table accuracy with VDDA = V to V.. 82 Table accuracy with VDDA = VREF+ = V to V .. 82 Table max for fADC = 16 MHz .. 84 List of tablesSTM8L051F36/96DS9178 Rev 4 Table data .. 86 Table data .. 86 Table absolute maximum ratings .. 87 Table sensitivities .. 87 Table 20-lead thin shrink small outline, x mm, mm pitch, package mechanical data .. 89 Table characteristics.. 92 Table revision history .. 94DS9178 Rev 47/96 STM8L051F3 List of figures7 List of figuresFigure block diagram .. 12 Figure clock tree diagram .. 17 Figure 20-pin TSSOP20 package pinout .. 23 Figure map .. 26 Figure loading conditions .. 45 Figure input voltage .. 46 Figure thresholds .. 50 Figure IDD(RUN) vs. VDD, fCPU = 16 MHz .. 52 Figure IDD(Wait) vs. VDD, fCPU = 16 MHz 1).. 54 Figure IDD(LPR) vs. VDD (LSI clock source) .. 55 Figure IDD(LPW) vs. VDD (LSI clock source) .. 56 Figure oscillator circuit diagram.

7 61 Figure oscillator circuit diagram .. 62 Figure HSI frequency vs VDD.. 63 Figure LSI frequency vs. VDD .. 64 Figure VIL and VIH vs VDD (high sink I/Os) .. 68 Figure VIL and VIH vs VDD (true open drain I/Os) .. 68 Figure pull-up resistance RPU vs VDD with VIN=VSS .. 69 Figure pull-up current Ipu vs VDD with VIN=VSS .. 69 Figure VOL @ VDD = V (high sink ports) .. 71 Figure VOL @ VDD = V (high sink ports) .. 71 Figure VOL @ VDD = V (true open drain ports) .. 71 Figure VOL @ VDD = V (true open drain ports) .. 71 Figure VDD - VOH @ VDD = V (high sink ports) .. 71 Figure VDD - VOH @ VDD = V (high sink ports) .. 71 Figure NRST pull-up resistance RPU vs VDD .. 72 Figure NRST pull-up current Ipu vs VDD .. 73 Figure NRST pin configuration .. 73 Figure timing diagram - slave mode and CPHA=0 .. 75 Figure timing diagram - slave mode and CPHA=1(1) .. 75 Figure timing diagram - master mode(1).

8 76 Figure application with I2C bus and timing diagram 1) .. 78 Figure accuracy characteristics .. 83 Figure connection diagram using the ADC .. 83 Figure dynamic current consumption on VREF+ supply pin during ADC conversion .. 83 Figure supply and reference decoupling (VREF+ not connected to VDDA).. 84 Figure supply and reference decoupling (VREF+ connected to VDDA) .. 85 Figure 20-lead thin shrink small outline, x mm, mm pitch, package outline.. 89 Figure 20-lead thin shrink small outline, x mm, mm pitch, package footprint .. 90 Figure marking for TSSOP20 20-lead thin shrink small outline, x mm, mm pitch example .. 91 Figure density value line STM8L051F3 ordering information scheme .. 93 IntroductionSTM8L051F38/96DS9178 Rev 41 IntroductionThis document describes the features, pinout, mechanical data and ordering information for the low density STM8L051F3 microcontroller with 8-Kbyte Flash memory further details on the whole STMicroelectronics low density family please refer to Section : Ultra-low-power detailed information on device operation and registers, refer to the STM8L050J3, STM8L051F3 , STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).

9 For information on to the Flash program memory and data EEPROM, refer to the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054).For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).The low density value line devices, including STM8L051F3 , provide the following benefits: Integrated system 8 Kbytes of low-density embedded Flash program memory 256 bytes of data EEPROM 1 Kbyte of RAM Internal high-speed and low-power low speed RC Embedded reset Ultra-low-power consumption 1 A in Active-halt mode Clock gated system and optimized power management Capability to execute from RAM for Low-power wait mode and Low-power run mode Advanced features Up to 16 MIPS at 16 MHz CPU clock frequency Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access Short development cycles Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals Wide choice of development toolsThese features make STM8L051F3 suitable for a wide range of consumer and mass market to Ta b l e 1: STM8L051F3 features and peripheral counts and Section 3.

10 Functional overview for an overview of the complete range of peripherals proposed in this 1 shows the block diagram of the low density STM8L051F3 device. DS9178 Rev 49/96 STM8L051F3 Description412 DescriptionSTM8L051F3 is member of the STM8L ultra-low-power 8-bit features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations. The STM8L051F3 MCU includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming. It features an embedded data EEPROM and low-power, low-voltage, single-supply program Flash device incorporates an extensive range of enhanced I/Os and peripherals, a 12-bit ADC, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an SPI, an I2C interface, and one modular design of the peripheral set allows this device to have the same peripherals that can be found in different ST microcontroller families including 32-bit families.